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preliminary information amd-k6 processor data sheet ?
preliminary information ? 1998 advanced micro devices, inc . all rights reserved. advanced micro devices, inc. (amd) reserves the right to make changes in its products without notice in order to improve design or performance characteristics. the information in this publication is believed to be accurate at the time of publication, but amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. amd disclaims responsibility for any consequences resulting from the use of the information included in this publication. this publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. amd products are not authorized for use as critical components in life support devices or systems without amds written approval. amd assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of amd products, except as provided in amds terms and conditions of sale for such products. trademarks amd, the amd logo, and combinations thereof, k86, amd-k5, and the amd-k6 logo are trademarks, and risc86 and amd-k6 are registered trademarks of advanced micro devices, inc. microsoft and windows are registered trademarks, and windows nt is a trademark of microsoft corporation. netware is a registered trademark of novell, inc. mmx is a trademark and pentium is a registered trademark of intel corporation. the tap state diagram is reprinted from ieee std 1149.1-1990 ieee standard test access port and boundary-scan architecture, copyright ? 1990 by the institute of electrical and electronics engineers, inc. the ieee disclaims any responsibility or liability resulting from the placement and use in the described manner. information is reprinted with the permission of the ieee. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
contents iii 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii about this data sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part one amd-k6 ? processor family 3 1 amd-k6 ? processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 internal architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 amd-k6 ? processor microarchitecture overview . . . . . . . . . 7 enhanced risc86 ? microarchitecture . . . . . . . . . . . . . . . . . . . 8 2.3 cache, instruction prefetch, and predecode bits . . . . . . . . . 11 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 predecode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 instruction fetch and decode . . . . . . . . . . . . . . . . . . . . . . . . . 13 instruction fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 instruction decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 centralized scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 branch-prediction logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 branch history table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 branch target cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 return address stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 branch execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 software environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 general-purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 integer data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 segment registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 segment usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 instruction pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 floating-point registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 floating-point register data types . . . . . . . . . . . . . . . . . . . . . 28 mmx? registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 eflags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 debug registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 model-specific registers (msr) . . . . . . . . . . . . . . . . . . . . . . . 37
iv contents amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information memory management registers . . . . . . . . . . . . . . . . . . . . . . . 39 task state segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 descriptors and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2 instructions supported by the amd-k6 processor . . . . . . . . 49 4 logic symbol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.1 a20m# (address bit 20 mask) . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2 a[31:3] (address bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3 ads# (address strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.4 adsc# (address strobe copy) . . . . . . . . . . . . . . . . . . . . . . . . 81 5.5 ahold (address hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.6 ap (address parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.7 apchk# (address parity check) . . . . . . . . . . . . . . . . . . . . . . 84 5.8 be[7:0]# (byte enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.9 bf[2:0] (bus frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.10 boff# (backoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.11 brdy# (burst ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.12 brdyc# (burst ready copy) . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.13 breq (bus request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.14 cache# (cacheable access) . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.15 clk (clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.16 d/c# (data/code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.17 d[63:0] (data bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.18 dp[7:0] (data parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.19 eads# (external address strobe) . . . . . . . . . . . . . . . . . . . . . 94 5.20 ewbe# (external write buffer empty) . . . . . . . . . . . . . . . . . 95 5.21 ferr# (floating-point error) . . . . . . . . . . . . . . . . . . . . . . . . 96 5.22 flush# (cache flush) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.23 hit# (inquire cycle hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.24 hitm# (inquire cycle hit to modified line) . . . . . . . . . . . . 98 5.25 hlda (hold acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.26 hold (bus hold request) . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.27 ignne# (ignore numeric exception) . . . . . . . . . . . . . . . . . 100 5.28 init (initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.29 intr (maskable interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.30 inv (invalidation request) . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.31 ken# (cache enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.32 lock# (bus lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.33 m/io# (memory or i/o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.34 na# (next address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.35 nmi (non-maskable interrupt) . . . . . . . . . . . . . . . . . . . . . . . 106 5.36 pcd (page cache disable) . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.37 pchk# (parity check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.38 pwt (page writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
contents v 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.39 reset (reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.40 rsvd (reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.41 scyc (split cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.42 smi# (system management interrupt) . . . . . . . . . . . . . . . . 111 5.43 smiact# (system management interrupt active) . . . . . . 112 5.44 stpclk# (stop clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.45 tck (test clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.46 tdi (test data input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.47 tdo (test data output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.48 tms (test mode select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.49 trst# (test reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.50 vcc2det (v cc2 detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.51 w/r# (write/read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.52 wb/wt# (writeback or writethrough) . . . . . . . . . . . . . . . . 116 6 bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.2 bus state machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . 123 idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 data-na# requested. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 pipeline address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 pipeline data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 6.3 memory reads and writes . . . . . . . . . . . . . . . . . . . . . . . . . . 126 single-transfer memory read and write . . . . . . . . . . . . . . . 126 misaligned single-transfer memory read and write . . . . . 128 burst reads and pipelined burst reads . . . . . . . . . . . . . . . . 130 burst writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.4 i/o read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 basic i/o read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 misaligned i/o read and write . . . . . . . . . . . . . . . . . . . . . . . 135 6.5 inquire and bus arbitration cycles . . . . . . . . . . . . . . . . . . . 136 hold and hold acknowledge cycle . . . . . . . . . . . . . . . . . . . . 136 hold-initiated inquire hit to shared or exclusive line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 hold-initiated inquire hit to modified line . . . . . . . . . . . 140 ahold-initiated inquire miss. . . . . . . . . . . . . . . . . . . . . . . . 142 ahold-initiated inquire hit to shared or exclusive line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 ahold-initiated inquire hit to modified line . . . . . . . . . . 146 ahold restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 bus backoff (boff#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 locked cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 basic locked operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 locked operation with boff# intervention . . . . . . . . . . . . 154 interrupt acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
vi contents amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 6.6 special bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 basic special bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 shutdown cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 stop grant and stop clock states . . . . . . . . . . . . . . . . . . . . . 161 init-initiated transition from protected mode to real mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 7 power-on configuration and initialization . . . . . . . . . . . . . . 167 7.1 signals sampled during the falling transition of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 flush# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 bf[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 brdyc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 7.2 reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 7.3 state of processor after reset . . . . . . . . . . . . . . . . . . . . . . 168 output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 7.4 state of processor after init . . . . . . . . . . . . . . . . . . . . . . . . 170 8 cache organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 8.1 mesi states in the data cache . . . . . . . . . . . . . . . . . . . . . . . 172 8.2 predecode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 8.3 cache operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 cache-related signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 8.4 cache disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 8.5 cache-line fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 8.6 cache-line replacements . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 8.7 write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 write to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 write to a sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 write allocate limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 descriptions of the logic mechanisms and conditions . . . . 180 8.8 prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 8.9 cache states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.10 cache coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 inquire cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 internal snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 flush# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 wbinvd and invd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 cache-line replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 cache snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 8.11 writethrough vs. writeback coherency states . . . . . . . . . . 187 8.12 a20m# masking of cache accesses . . . . . . . . . . . . . . . . . . . 187 9 floating-point and multimedia execution units . . . . . . . . . 189 9.1 floating-point execution unit . . . . . . . . . . . . . . . . . . . . . . . 189 handling floating-point exceptions . . . . . . . . . . . . . . . . . . . 189 external logic support of floating-point exceptions . . . . . 189
contents vii 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 9.2 multimedia execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . 191 9.3 floating-point and mmx instruction compatibility . . . . . . 191 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 ferr# and ignne# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 10 system management mode (smm) . . . . . . . . . . . . . . . . . . . . 193 10.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 10.2 smm operating mode and default register values . . . . . 193 10.3 smm state-save area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.4 smm revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 10.5 smm base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 10.6 halt restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 10.7 i/o trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 10.8 i/o trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 10.9 exceptions, interrupts, and debug in smm . . . . . . . . . . . . 202 11 test and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 11.1 built-in self-test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 11.2 tri-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.3 boundary-scan test access port (tap) . . . . . . . . . . . . . . . . 205 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 tap signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 tap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 tap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 tap controller state machine . . . . . . . . . . . . . . . . . . . . . . . . 212 11.4 l1 cache inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 11.5 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 debug registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 debug exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 12 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.1 halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 enter halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 exit halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.2 stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 enter stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 exit stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.3 stop grant inquire state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 enter stop grant inquire state . . . . . . . . . . . . . . . . . . . . . . . 226 exit stop grant inquire state . . . . . . . . . . . . . . . . . . . . . . . . 226 12.4 stop clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 enter stop clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 exit stop clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
viii contents amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 13 power and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.1 power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.2 decoupling recommendations . . . . . . . . . . . . . . . . . . . . . . . 230 13.3 pin connection requirements . . . . . . . . . . . . . . . . . . . . . . . 231 14 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.1 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.2 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14.4 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 15 i/o buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.1 selectable drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.2 i/o buffer model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 15.3 i/o model application note . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.4 i/o buffer ac and dc characteristics . . . . . . . . . . . . . . . . . 239 16 signal switching characteristics . . . . . . . . . . . . . . . . . . . . . . 241 16.1 clk switching characteristics . . . . . . . . . . . . . . . . . . . . . . . 241 16.2 clock switching characteristics for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.3 clock switching characteristics for 60-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.4 valid delay, float, setup, and hold timings . . . . . . . . . . . 243 16.5 output delay timings for 66-mhz bus operation . . . . . . . 244 16.6 input setup and hold timings for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 16.7 output delay timings for 60-mhz bus operation . . . . . . . 248 16.8 input setup and hold timings for 60-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 16.9 reset and test signal timing . . . . . . . . . . . . . . . . . . . . . . 252 17 thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.1 package thermal specifications . . . . . . . . . . . . . . . . . . . . . . 259 heat dissipation path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 measuring case temperature . . . . . . . . . . . . . . . . . . . . . . . . 262 17.2 layout and airflow considerations . . . . . . . . . . . . . . . . . . . 262 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 airflow management in a system design . . . . . . . . . . . . . . . 264 18 pin description diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 19 pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 20 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 20.1 321-pin staggered cpga package specification . . . . . . . . 271 21 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
contents ix 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information part two amd-k6 processor model 7 275 22 amd-k6 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 23 internal architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 24 software environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 24.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 model-specific registers (msr) . . . . . . . . . . . . . . . . . . . . . . 281 24.2 instructions supported by the amd-k6 processor . . . . . . . 283 25 logic symbol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 26 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 26.1 vcc2det (v cc2 detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 26.2 vcc2h/l# (v cc2 high/low) . . . . . . . . . . . . . . . . . . . . . . . . . 287 27 bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 28 power-on configuration and initialization . . . . . . . . . . . . . . 291 28.1 state of processor after reset . . . . . . . . . . . . . . . . . . . . . . 291 output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 29 cache organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 30 floating-point and multimedia execution units . . . . . . . . . 295 31 system management mode (smm) . . . . . . . . . . . . . . . . . . . . 297 32 test and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 32.1 tri-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 32.2 boundary-scan test access port (tap) . . . . . . . . . . . . . . . . 299 tap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 33 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 34 power and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 34.1 power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 35 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 35.1 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 35.2 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 35.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 35.4 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 36 i/o buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
x contents amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 37 signal switching characteristics . . . . . . . . . . . . . . . . . . . . . . 311 38 thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 38.1 package thermal specifications . . . . . . . . . . . . . . . . . . . . . . 313 39 pin description diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 40 pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 41 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 42 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
list of figures xi 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information list of figures part one amd-k6 processor family 3 figure 1. amd-k6 processor block diagram . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. cache sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. the instruction buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. amd-k6 processor decode logic . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. amd-k6 processor scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. eax register with 16-bit and 8-bit name components. . . . . . 22 figure 7. integer data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. segment usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. floating-point register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. fpu status word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. fpu control word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 13. fpu tag word register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 14. packed decimal data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 15. precision real data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 16. mmx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 17. mmx data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18. eflags registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 19. control register 4 (cr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 20. control register 3 (cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 21. control register 2 (cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22. control register 1 (cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23. control register 0 (cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 24. debug register dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 25. debug register dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 26. debug registers dr5 and dr4. . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 27. debug registers dr3, dr2, dr1, and dr0. . . . . . . . . . . . . . . . 36 figure 28. machine-check address register (mcar) . . . . . . . . . . . . . . . . 37 figure 29. machine-check type register (mctr) . . . . . . . . . . . . . . . . . . . 38 figure 30. test register 12 (tr12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 31. time stamp counter (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 32. write handling control register (whcr) . . . . . . . . . . . . . . . . 39 figure 33. memory management registers . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 34. task state segment (tss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
xii list of figures amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 35. 4-kbyte paging mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 36. 4-mbyte paging mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 37. page directory entry 4-kbyte page table (pde) . . . . . . . . . . . 44 figure 38. page directory entry 4-mbyte page table (pde) . . . . . . . . . . 44 figure 39. page table entry (pte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 40. application segment descriptor . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 41. system segment descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 42. gate descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 43. waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 44. bus state machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 45. non-pipelined single-transfer memory read/write and write delayed by ewbe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 46. misaligned single-transfer memory read and write . . . . . . 129 figure 47. burst reads and pipelined burst reads . . . . . . . . . . . . . . . . . 131 figure 48. burst writeback due to cache-line replacement . . . . . . . . . 133 figure 49. basic i/o read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 50. misaligned i/o transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 51. basic hold/hlda operation . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 52. hold-initiated inquire hit to shared or exclusive line . . . 139 figure 53. hold-initiated inquire hit to modified line. . . . . . . . . . . . . 141 figure 54. ahold-initiated inquire miss . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 55. ahold-initiated inquire hit to shared or exclusive line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 56. ahold-initiated inquire hit to modified line . . . . . . . . . . . 147 figure 57. ahold restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 58. boff# timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 59. basic locked operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 60. locked operation with boff# intervention. . . . . . . . . . . . . . 155 figure 61. interrupt acknowledge operation . . . . . . . . . . . . . . . . . . . . . . 157 figure 62. basic special bus cycle (halt cycle) . . . . . . . . . . . . . . . . . . . . 159 figure 63. shutdown cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 64. stop grant and stop clock modes, part 1 . . . . . . . . . . . . . . . . 162 figure 65. stop grant and stop clock modes, part 2 . . . . . . . . . . . . . . . . 163 figure 66. init-initiated transition from protected mode to real mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 67. cache organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 68. cache sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 69. write handling control register (whcr) . . . . . . . . . . . . . . . 179 figure 70. write allocate logic mechanisms and conditions . . . . . . . . . 180 figure 71. external logic for supporting floating-point exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
list of figures xiii 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 72. smm memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 73. tap state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 74. debug register dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 75. debug register dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 76. debug registers dr5 and dr4. . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 77. debug registers dr3, dr2, dr1, and dr0. . . . . . . . . . . . . . . 219 figure 78. clock control state transitions . . . . . . . . . . . . . . . . . . . . . . . . 228 figure 79. suggested component placement . . . . . . . . . . . . . . . . . . . . . . 230 figure 80. k6std pulldown v/i curves . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 figure 81. k6std pullup v/i curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 figure 82. clk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 figure 83. diagrams key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 figure 84. output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 figure 85. maximum float delay timing . . . . . . . . . . . . . . . . . . . . . . . . . 255 figure 86. input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . 255 figure 87. reset and configuration timing . . . . . . . . . . . . . . . . . . . . . . . 256 figure 88. tck waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 figure 89. trst# timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 figure 90. test signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 figure 91. thermal model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 figure 92. power consumption vs. thermal resistance . . . . . . . . . . . . . 260 figure 93. processor heat dissipation path . . . . . . . . . . . . . . . . . . . . . . . 261 figure 94. measuring case temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 262 figure 95. voltage regulator placement . . . . . . . . . . . . . . . . . . . . . . . . . . 263 figure 96. airflow for a heatsink with fan . . . . . . . . . . . . . . . . . . . . . . . . 263 figure 97. airflow path in a dual-fan system . . . . . . . . . . . . . . . . . . . . . . 264 figure 98. airflow path in an atx form-factor system . . . . . . . . . . . . . 265 figure 99. amd-k6 processor top-side view . . . . . . . . . . . . . . . . . . . . . . 267 figure 100. amd-k6 processor pin-side view . . . . . . . . . . . . . . . . . . . . . . 268 figure 101. 321-pin staggered cpga package specification . . . . . . . . . . 272 part two amd-k6 processor model 7 275 figure 102. extended feature enable register (efer) . . . . . . . . . . . . . . 282 figure 103. syscall/sysret target address register (star) . . . . . . 283 figure 104. amd-k6 processor model 7 top-side view. . . . . . . . . . . . . . . 315 figure 105. amd-k6 processor model 7 pin-side view . . . . . . . . . . . . . . . 316
xiv list of figures amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
list of tables xv 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information list of tables part one amd-k6 processor family 3 table 1. execution latency and throughput of execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 2. general-purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 3. general-purpose register dword, word, and byte names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 4. segment registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5. model-specific registers (msrs) . . . . . . . . . . . . . . . . . . . . . . . . 37 table 6. memory management registers . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 7. application segment types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 8. system segment and gate types . . . . . . . . . . . . . . . . . . . . . . . . 47 table 9. summary of exceptions and interrupts . . . . . . . . . . . . . . . . . . . 48 table 10. integer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 11. floating-point instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 12. mmx instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 13. processor-to-bus clock ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 14. input pin types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 15. output pin float conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 16. input/output pin float conditions. . . . . . . . . . . . . . . . . . . . . . 118 table 17. test pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 18. bus cycle definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 19. special cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 20. bus-cycle order during misaligned transfers . . . . . . . . . . . . 128 table 21. a[4:3] address-generation sequence during bursts . . . . . . . 130 table 22. bus-cycle order during misaligned i/o transfers . . . . . . . . . 135 table 23. interrupt acknowledge operation definition. . . . . . . . . . . . . 156 table 24. encodings for special bus cycles . . . . . . . . . . . . . . . . . . . . . . 158 table 25. output signal state after reset . . . . . . . . . . . . . . . . . . . . . . 168 table 26. register state after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 27. pwt signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 28. pcd signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 29. cache# signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 30. data cache states for read and write accesses . . . . . . . . . . 182 table 31. cache states for inquiries, snoops, invalidation, and replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 32. snoop action. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 33. initial state of registers in smm . . . . . . . . . . . . . . . . . . . . . . . 195 table 34. smm state-save area map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 35. smm revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 36. i/o trap dword configuration . . . . . . . . . . . . . . . . . . . . . . . . . 200
xvi list of tables amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information table 37. i/o trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 38. boundary scan bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 39. device identification register . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 40. supported tap instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 41. dr7 len and rw definitions . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 42. operating ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 table 43. absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 table 44. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 table 45. typical and maximum power dissipation . . . . . . . . . . . . . . . . 235 table 46. a[20:3], ads#, hitm#, and w/r# strength selection . . . . . . 237 table 47. clk switching characteristics for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 48. clk switching characteristics for 60-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 49. output delay timings for 66-mhz bus operation . . . . . . . . . 244 table 50. input setup and hold timings for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 table 51. output delay timings for 60-mhz bus operation . . . . . . . . . 248 table 52. input setup and hold timings for 60-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 table 53. reset and configuration signals (60-mhz and 66-mhz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 table 54. tck waveform and trst# timing at 25 mhz . . . . . . . . . . . . 253 table 55. test signal timing at 25 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . 253 table 56. package thermal specification . . . . . . . . . . . . . . . . . . . . . . . . 259 table 57. 321-pin staggered cpga package specification . . . . . . . . . . 271 table 58. valid ordering part number combinations . . . . . . . . . . . . . . 273 part two amd-k6 processor model 7 275 table 59. model-specific registers (msrs) . . . . . . . . . . . . . . . . . . . . . . . 282 table 60. extended feature enable register (efer) definition . . . . . 282 table 61. syscall/sysret target address register (star) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 table 62. integer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 table 63. output pin float conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 table 64. output signal state after reset . . . . . . . . . . . . . . . . . . . . . . 291 table 65. register state after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 table 66. device identification register . . . . . . . . . . . . . . . . . . . . . . . . . 300 table 67. operating ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 table 68. absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 table 69. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 table 70. typical and maximum power dissipation . . . . . . . . . . . . . . . . 307 table 71. package thermal specification . . . . . . . . . . . . . . . . . . . . . . . . 313 table 72. valid ordering part number combinations . . . . . . . . . . . . . . 321
revision history xvii 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information revision history date rev description june 1997 e replaced overbar with # to identify active-low signals. june 1997 e corrected description in write allocate on page 177. june 1997 e revised latency and throughput information in table 1, execution latency and throughput of execution units, on page 18. june 1997 e updated figure 79, suggested component placement, on page 230 of chapter 13, power and grounding. sept 1997 f unreleased version. march 1998 g divided book into part 1 and part 2. part 1 provides information about the amd-k6 ? processor family (model 6 and model 7) and part 2 provides information specific to the amd-k6 processor model 7 (0.25-micron process technology). march 1998 g added figure 17, mmx? data types, on page 30 in chapter 3, software environment. march 1998 g qualified conditions under which write allocate occurs in the memory area between 640 kbytes and 1 mbyte in write allocate limit on page 178 of chapter 8, cache organization. march 1998 g changed power dissipation specifications for stop grant state and stop clock state for 166mhz, 200mhz, and 233mhz components in table 45, typical and maximum power dissipation, on page 235, and table 56, package thermal specification, on page 259. march 1998 g removed all references to write ken# control register (wkcr) from chapter 3, software environment, chapter 5, signal descriptions, and chapter 8, cache organization. march 1998 g added top-side view pin description diagram. see figure 99, amd-k6 ? processor top-side view , on page 267. march 1998 g added voltage detection pin to diagram in chapter 4, logic symbol diagram. march 1998 g modified flatness specification (symbol f) in table 57, 321-pin staggered cpga package specification, on page 271. march 1998 g corrected figure 44, bus state machine diagram, on page 123 in chapter 6, bus cycles to accurately show the direct transition from the pipeline data state to the data-na# requested state. march 1998 g corrected list of internal resources tested during bist in chapter 11, test and debug on page 203. march 1998 g revised figure 92, power consumption vs. thermal resistance, on page 260 in chapter 17, thermal design. march 1998 h revised signal description of vcc2h/l# on page 287 in chapter 26, signal descriptions.
xviii revision history amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
about this data sheet 1 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information about this data sheet the amd-k6 ? processor data sheet supports the model 6 and model 7 versions of the amd-k6 processor family. model 6 refers to the amd-k6 manufactured in the 0.35-micron process technology and model 7 refers to the amd-k6 manufactured in the 0.25-micron process technology. the data sheet is divided into two parts. part one (chapters 1C21) contains information that pertains to the entire amd-k6 desktop family and information specific to the model 6. part two (chapters 22C42) contains information regarding new specifications and differences that pertain only to model 7 as compared to model 6.
2 about this data sheet amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
20695h/0march 1998 amd-k6 ? processor data sheet preliminary information part one amd-k6 ? processor family 3 part one amd-k6 processor family the amd-k6 ? processor data sheet supports the model 6 and model 7 versions of the amd-k6 processor family. model 6 refers to the amd-k6 manufactured with 0.35-micron process technology and model 7 refers to the amd-k6 manufactured with 0.25-micron process technology. part one (chapters 1 C21) contains information that pertains to the entire amd-k6 desktop family and information specific to model 6. ?
4 amd-k6 ? processor family part one amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
20695h/0march 1998 amd-k6 ? processor data sheet preliminary information chapter 1 amd-k6 ? processor 5 1amd-k6 ? processor n advanced 6-issue risc86 ? superscalar microarchitecture u seven parallel specialized execution units u multiple sophisticated x86-to-risc86 instruction decoders u advanced two-level branch prediction u speculative execution u out-of-order execution u register renaming and data forwarding u issues up to six risc86 instructions per clock n large on-chip split 64-kbyte level-one (l1) cache u 32-kbyte instruction cache with additional predecode cache u 32-kbyte writeback dual-ported data cache u mesi protocol support n high-performance ieee 754-compatible and 854-compatible floating-point unit n high-performance industry-standard mmx? instructions n 321-pin ceramic pin grid array (cpga) package (socket 7 compatible) n industry-standard system management mode (smm) n ieee 1149.1 boundary scan n full x86 binary software compatibility as the next generation in the amd k86? family of x86 processors, the innovative amd-k6 processor brings industry-leading performance to pc systems running the extensive installed base of x86 software. in addition, its socket 7 compatible, 321-pin ceramic pin grid array (cpga) package enables the amd-k6 to reduce time-to-market by leveraging todays cost-effective infrastructure to deliver a superior price/performance pc solution. to provide state-of-the-art performance, the amd-k6 processor incorporates the innovative and efficient risc86 microarchitecture, a large 64-kbyte level-one cache (32-kbyte dual-ported data cache, 32-kbyte instruction cache with predecode data), a powerful ieee 754-compatible and 854-compatible floating-point execution unit, and a high-performance multimedia execution unit for executing industry-standard mmx instructions. these features have been combined to deliver industry leadership in 16-bit and 32-bit performance, providing exceptional performance for both windows ? 95 and windows nt? software bases.
6 amd-k6 ? processor chapter 1 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information the amd-k6 processors risc86 microarchitecture is a decoupled decode/execution superscalar design that implements state-of-the-art design techniques to achieve leading-edge performance. advanced design techniques implemented in the amd-k6 include multiple x86 instruction decode, single-clock internal risc operations, seven execution units that support superscalar operation, out-of-order execution, data forwarding, speculative execution, and register renaming. in addition, the processor supports the industrys most advanced branch prediction logic by implementing an 8192-entry branch history table, the industrys only branch target cache, and a return address stack, which combine to deliver better than a 95% prediction rate. these design techniques enable the amd-k6 processor to issue, execute, and retire multiple x86 instructions per clock, resulting in excellent scaleable performance. the amd-k6 processor is fully x86 binary code compatible. amds extensive experience through four generations of x86 processors has been carefully integrated into the amd-k6 to provide complete compatibility with windows 95, windows 3.x, windows nt, dos, os/2, unix, solaris, netware ? , vines, and other leading x86 operating systems and applications. the amd-k6 processor is socket 7 compatible, allowing the processor to be quickly and easily integrated into a mature and cost-effective industry-standard infrastructure of motherboards, chipsets, power supplies, and thermal designs. amd has designed, manufactured, and delivered over 50 million microsoft ? windows-compatible processors in the last five years alone. the amd-k6 processor is the next generation in this long line of processors. with its combination of state-of-the-art features, industry-leading performance, high-performance multimedia engine, full x86 compatibility, and low-cost infrastructure, the amd-k6 is the superior choice for mainstream personal computers.
chapter 2 internal architecture 7 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 2 internal architecture 2.1 introduction the amd-k6 processor implements advanced design techniques known as the risc86 microarchitecture. the risc86 microarchitecture is a decoupled decode/execution design approach that yields superior sixth-generation performance for x86-based software. this chapter describes the techniques used and the functional elements of the risc86 microarchitecture. 2.2 amd-k6 ? processor microarchitecture overview when discussing processor design, it is important to understand the terms architecture , microarchitecture , and design implementation . the term architecture refers to the instruction set and features of a processor that are visible to software programs running on the processor. the architecture determines what software the processor can run. the architecture of the amd-k6 processor is the industry-standard x86 instruction set. the term microarchitecture refers to the design techniques used in the processor to reach the target cost, performance, and functionality goals. the amd-k6 is based on a sophisticated risc core known as the enhanced risc86 microarchitecture. the enhanced risc86 microarchitecture is an advanced, second-order decoupled decode/execution design approach that enables industry-leading performance for x86-based software. the term design implementation refers to the actual logic and circuit designs from which the processor is created according to the microarchitecture specifications.
8 internal architecture chapter 2 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information enhanced risc86 ? microarchitecture the enhanced risc86 microarchitecture defines the characteristics of the amd-k6. the innovative risc86 microarchitecture approach implements the x86 instruction set by internally translating x86 instructions into risc86 operations. these risc86 operations were specially designed to include direct support for the x86 instruction set while observing the risc performance principles of fixed length encoding, regularized instruction fields, and a large register set. the enhanced risc86 microarchitecture used in the amd-k6 enables higher processor core performance and promotes straightforward extensibility in future designs. instead of directly executing complex x86 instructions, which have lengths of 1 to 15 bytes, the amd-k6 processor executes the simpler and easier fixed-length risc86 opcodes, while maintaining the instruction coding efficiencies found in x86 programs. the amd-k6 processor contains parallel decoders, a centralized risc86 operation scheduler, and seven execution units that support superscalar operationmultiple decode, execution, and retirementof x86 instructions. these elements are packed into an aggressive and highly efficient six-stage pipeline. decoders. decoding of the x86 instructions begins when the on-chip instruction cache is filled. predecode logic determines the length of an x86 instruction on a byte-by-byte basis. this predecode information is stored, along with the x86 instructions, in the instruction cache, to be used later by the decoders. the decoders translate on-the-fly, with no additional latency, up to two x86 instructions per clock into risc86 operations. note: in this chapter, clock refers to a processor clock. the amd-k6 processor categorizes x86 instructions into three types of decodesshort, long and vector. the decoders process either two short, one long, or one vector decode at a time. the three types of decodes have the following characteristics: n short decodesx86 instructions less than or equal to seven bytes in length n long decodesx86 instructions less than or equal to 11 bytes in length n vector decodescomplex x86 instructions
chapter 2 internal architecture 9 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information short and long decodes are processed completely within the decoders. vector decodes are started by the decoders and then completed by fetched sequences from an on-chip rom. after decoding, the risc86 operations are delivered to the scheduler for dispatching to the executions units. scheduler/instruction control unit. the centralized scheduler or buffer is managed by the instruction control unit (icu). the icu buffers and manages up to 24 risc86 operations at a time. this equals from 6 to 12 x86 instructions. this buffer size (24) is perfectly matched to the processors six-stage risc86 pipeline and seven parallel execution units. the scheduler accepts as many as four risc86 operations at a time from the decoders. the icu is capable of simultaneously issuing up to six risc86 operations at a time to the execution units. this consists of the following types of operations: n memory load operation n memory store operation n complex integer or mmx register operation n simple integer register operation n floating-point register operation n branch condition evaluation registers. the scheduler uses 48 physical registers that are contained within the risc86 microarchitecture when managing the 24 risc86 operations. the 48 physical registers are located in a general register file and are grouped as 24 general registers, plus 24 renaming registers. the 24 general registers consist of 16 scratch registers and eight registers that correspond to the x86 general purpose registerseax, ebx, ecx, edx, ebp, esp, esi and edi. branch logic. the amd-k6 processor is designed with highly sophisticated dynamic branch logic consisting of the following: n branch history/prediction table n branch target cache n return address stack the amd-k6 implements a two-level branch prediction scheme based on an 8192-entry branch history table. the branch history table stores prediction information that is used for predicting conditional branches. because the branch history table does not
10 internal architecture chapter 2 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information store predicted target addresses, special address alus calculate target addresses on-the-fly during instruction decode. the branch target cache augments predicted branch performance by avoiding a one clock cache-fetch penalty. this specialized target cache does this by supplying the first 16 bytes of target instructions to the decoders when branches are predicted. the return address stack is a unique device specifically designed for optimizing call and return pairs. in summary, the amd-k6 uses dynamic branch logic to minimize delays due to the branch instructions that are common in x86 software. amd-k6 ? processor block diagram. as shown in figure 1 on page 11, the high-performance, out-of-order execution engine of the amd-k6 processor is mated to a split level-one 64-kbyte writeback cache with 32 kbytes of instruction cache and 32 kbytes of data cache. the instruction cache feeds the decoders and, in turn, the decoders feed the scheduler. the icu issues and retires risc86 operations contained in the scheduler. the system bus interface is an industry-standard 64-bit pentium ? processor demultiplexed bus. the amd-k6 processor combines the latest in processor microarchitecture to provide the highest x86 performance for todays personal computers. the amd-k6 offers true sixth-generation performance and full x86 binary software compatibility.
chapter 2 internal architecture 11 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 1. amd-k6 ? processor block diagram 2.3 cache, instruction prefetch, and predecode bits the writeback level-one cache on the amd-k6 processor is organized as a separate 32-kbyte instruction cache and a 32-kbyte data cache with two-way set associativity. the cache line size is 32 bytes and lines are prefetched from main memory using an efficient pipelined burst transaction. as the instruction cache is filled, each instruction byte is analyzed for instruction boundaries using predecoding logic. predecoding annotates each instruction byte with information that later enables the decoders to efficiently decode multiple instructions simultaneously. cache the processor cache design takes advantage of a sectored organization (see figure 2 on page 12). each sector consists of 64 bytes configured as two 32-byte cache lines. the two cache lines of a sector share a common tag but have separate pairs of mesi (modified, exclusive, shared, invalid) bits that track the state of each cache line. integer x (register) unit store unit integer y (register) unit floating-point unit branch (resolving) unit store queue instruction control unit scheduler buffer (24 risc86) six risc86 ? operation issue out-of-order execution engine level-one dual-port data cache (32 kbyte) 128-entry dtlb level-one instruction cache (32 kbyte + predecode) 64-entry itlb dual instruction decoders x86 to risc86 branch logic (8192-entry bht) (16-entry btc) (16-entry ras) load unit multimedia unit predecode logic level-one cache controller socket 7 bus interface 16-byte fetch four risc86 decode
12 internal architecture chapter 2 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 2. cache sector organization two forms of cache misses and associated cache fills can take placea sector replacement and a cache line replacement. in the case of a sector replacement, the miss is due to a tag mismatch, in which case the required cache line is filled from external memory, and the cache line within the sector that was not required is marked as invalid. in the case of a cache line replacement, the address matches the tag, but the requested cache line is marked as invalid. the required cache line is filled from external memory, and the cache line within the sector that is not required remains in the same cache state. prefetching the amd-k6 processor performs cache prefetching for sector replacements onlyas opposed to cache line replacements. this cache prefetching results in the filling of the required cache line first, and a prefetch of the second cache line. furthermore, the prefetch of the cache line that is not required is initiated only in the forward directionthat is, only if the requested cache line is the first cache line within the sector. from the perspective of the external bus, the two cache-line fills typically appear as two 32-byte burst read cycles occurring back-to-back or, if allowed, as pipelined cycles. predecode bits decoding x86 instructions is particularly difficult because the instructions are variable-length and can be from 1 to 15 bytes long. predecode logic supplies the predecode bits that are associated with each instruction byte. the predecode bits indicate the number of bytes to the start of the next x86 instruction. the predecode bits are stored in an extended instruction cache alongside each x86 instruction byte as shown in figure 2 on page 12. the predecode bits are passed with the instruction bytes to the decoders where they assist with parallel x86 instruction decoding. tag address cache line 1 byte 31 predecode bits byte 30 predecode bits ........ ........ byte 0 predecode bits mesi bits cache line 2 byte 31 predecode bits byte 30 predecode bits ........ ........ byte 0 predecode bits mesi bits
chapter 2 internal architecture 13 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 2.4 instruction fetch and decode instruction fetch the processor can fetch up to 16 bytes per clock out of the instruction cache or branch target cache. the fetched information is placed into a 16-byte instruction buffer that feeds directly into the decoders (see figure 3). fetching can occur along a single execution stream with up to seven outstanding branches taken. the instruction fetch logic is capable of retrieving any 16 contiguous bytes of information within a 32-byte boundary. there is no additional penalty when the 16 bytes of instructions lie across a cache line boundary. the instruction bytes are loaded into the instruction buffer as they are consumed by the decoders. although instructions can be consumed with byte granularity, the instruction buffer is managed on a memory-aligned word (2 bytes) organization. therefore, instructions are loaded and replaced with word granularity. when a control transfer occurssuch as a jmp instruction the entire instruction buffer is flushed and reloaded with a new set of 16 instruction bytes. figure 3. the instruction buffer 16 instruction bytes plus 16 sets of predecode bits branch-target cache 16 x 16 by tes 2:1 instruction buffer 16 bytes 16 bytes branch target address adders return address stack 16 x 16 bytes 32-kbyte level-one instruction cache fetch unit
14 internal architecture chapter 2 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information instruction decode the amd-k6 processor decode logic is designed to decode multiple x86 instructions per clock (see figure 4). the decode logic accepts x86 instruction bytes and their predecode bits from the instruction buffer, locates the actual instruction boundaries, and generates risc86 operations from these x86 instructions. risc86 operations are fixed-format internal instructions. most risc86 operations execute in a single clock. risc86 operations are combined to perform every function of the x86 instruction set. some x86 instructions are decoded into as few as zero risc86 opcodes for instance a nopor one risc86 operationa register-to-register add. more complex x86 instructions are decoded into several risc86 operations. figure 4. amd-k6 ? processor decode logic instruction buffer 4 risc86 operations on-chip rom long decoder short decoder #1 short decoder #2 vector address vector decoder risc86 ? sequencer
chapter 2 internal architecture 15 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information the amd-k6 processor uses a combination of decoders to convert x86 instructions into risc86 operations. the hardware consists of three sets of decoders two parallel short decoders, one long decoder, and one vectoring decoder. the parallel short decoders translate the most commonly-used x86 instructions (moves, shifts, branches, alu, mmx, fpu) into zero, one, or two risc86 operations each. the short decoders only operate on x86 instructions that are up to seven bytes long. in addition, they are designed to decode up to two x86 instructions per clock. the commonly-used x86 instructions that are greater than seven bytes but not more than 11 bytes long, and semi-commonly-used x86 instructions that are up to seven bytes long are handled by the long decoder. the long decoder only performs one decode per clock and generates up to four risc86 operations. all other translations (complex instructions, serializing conditions, interrupts and exceptions, etc.) are handled by a combination of the vector decoder and risc86 operation sequences fetched from an on-chip rom. for complex operations, the vector decoder logic provides the first set of risc86 operations and a vector (initial rom address) to a sequence of further risc86 operations. the same types of risc86 operations are fetched from the rom as those that are generated by the hardware decoders. note: although all three sets of decoders are simultaneously fed a copy of the instruction buffer contents, only one of the three types of decoders is used during any one decode clock. the decoders or the risc86 sequencer always generate a group of four risc86 operations. for decodes that cannot fill the entire group with four risc86 operations, risc86 nop operations are placed in the empty locations of the grouping. for example, a long-decoded x86 instruction that converts to only three risc86 operations is padded with a single risc86 nop operation and then passed to the scheduler. up to six groups or 24 risc86 operations can be placed in the scheduler at a time. all of the common, and a few of the uncommon, floating-point instructions (also known as esc instructions) are hardware decoded as short decodes. this decode generates a risc86 floating-point operation and, optionally, an associated floating-point load or store operation. floating-point or esc instruction decode is only allowed in the first short decoder, but non-esc instructions, excluding mmx instructions, can be
16 internal architecture chapter 2 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information decoded simultaneously by the second short decoder along with an esc instruction decode in the first short decoder. all of the mmx instructions, with the exception of the emms instruction, are hardware decoded as short decodes. the mmx instruction decode generates a risc86 mmx operation and, optionally, an associated mmx load or store operation. mmx instruction decode is only allowed in the first short decoder. however, instructions other than mmx and esc instructions can be decoded simultaneously by the second short decoder along with an mmx instruction decode in the first short decoder. 2.5 centralized scheduler the scheduler is the heart of the amd-k6 processor (see figure 5 on page 17). it contains the logic necessary to manage out-of-order execution, data forwarding, register renaming, simultaneous issue and retirement of multiple risc86 operations, and speculative execution. t he schedulers buffer can hold up to 24 risc86 operations. this equates to a maximum of 12 x86 instructions. when possible, the scheduler can simultaneously issue a risc86 operation to any available execution unit (store, load, branch, integer, integer/multimedia, or floating-point). in total, the scheduler can issue up to six and retire up to four risc86 operations per clock. the main advantage of the scheduler and its operation buffer is the ability to examine an x86 instruction window equal to 12 x86 instructions at one time. this advantage is due to the fact that the scheduler operates on the risc86 operations in parallel and allows the amd-k6 processor to perform dynamic on-the-fly instruction code scheduling for optimized execution. although the scheduler can issue risc86 operations for out-of-order execution, it always retires x86 instructions in order.
chapter 2 internal architecture 17 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 5. amd-k6 ? processor scheduler 2.6 execution units the amd-k6 processor contains seven execution units store, load, integer x, integer y, multimedia, floating-point, and branch condition. each unit is independent and capable of handling the risc86 operations. table 1 on page 18 details the execution units, functions performed within these units, operation latency, and operation throughput. the store and load execution units are two-staged pipelined designs. the store unit performs data writes and register calculation for lea/push. data memory and register writes from stores are available after one clock. the load unit performs data memory reads. data is available from the load unit after two clocks. the integer x execution unit can operate on all alu operations, multiplies, divides (signed and unsigned), shifts, and rotates. risc86 operation buffer risc86 issue buses risc86 #0 risc86 #1 risc86 #2 risc86 #3 centralized risc86 ? operation scheduler from decode logic
18 internal architecture chapter 2 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information the multimedia unit shares pipeline control with the integer x unit and executes all mmx instructions. the integer y execution unit can operate on the basic word and doubleword alu operations add, and, cmp, or, sub, xor, zero-extend and sign-extend operands. the branch condition unit is separate from the branch prediction logic in that it resolves conditional branches such as jcc and loop after the branch condition has been evaluated. table 1. execution latency and throughput of execution units execution unit function latency throughput store lea/push, address 1 1 memory store 1 1 load memory loads 2 1 integer x integer alu 1 1 integer multiply 2C3 2C3 integer shift 1 1 multimedia mmx alu 1 1 mmx shifts, packs, unpack 1 1 mmx multiply 1C2 1C2 integer y basic alu (16 - & 32-bit operands) 11 branch resolves branch conditions 1 1 fpu fadd, fsub, fmul 2 2
chapter 2 internal architecture 19 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 2.7 branch-prediction logic sophisticated branch logic that can minimize or hide the impact of changes in program flow is designed into the amd-k6 processor. branches in x86 code fit into two categories unconditional branches, which always change program flow (that is, the branches are always taken) and conditional branches, which may or may not divert program flow (that is, the branches are taken or not-taken). when a conditional branch is not taken, the processor simply continues decoding and executing the next instructions in memory. typical applications have up to 10% of unconditional branches and another 10% to 20% conditional branches. the amd-k6 branch logic has been designed to handle this type of program behavior and its negative effects on instruction execution, such as stalls due to delayed instruction fetching and the draining of the processor pipeline. the branch logic contains an 8192-entry branch history table, a 16-entry by 16-byte branch target cache, a 16-entry return address stack, and a branch execution unit. branch history table the amd-k6 processor handles unconditional branches without any penalty by redirecting instruction fetching to the target address of the unconditional branch. however, conditional branches require the use of the dynamic branch-prediction mechanism built into the amd-k6. a two-level adaptive history algorithm is implemented in an 8192-entry branch history table. this table stores executed branch information, predicts individual branches, and predicts the behavior of groups of branches. to accommodate the large branch history table, the amd-k6 processor does not store predicted target addresses. instead, the branch target addresses are calculated on-the-fly using alus during the decode stage. the adders calculate all possible target addresses before the instructions are fully decoded and the processor chooses which addresses are valid. branch target cache to avoid a one clock cache-fetch penalty when a branch is predicted taken, a built-in branch target cache supplies the first 16 bytes of instructions directly to the instruction buffer (assuming the target address hits this cache). (see figure 3 on page 13.) the branch target cache is organized as 16 entries of 16 bytes. in total, the branch prediction logic achieves branch prediction rates greater than 95%.
20 internal architecture chapter 2 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information return address stack the return address stack is a special device designed to optimize call and ret pairs. software is typically compiled with subroutines that are frequently called from various places in a program. this is usually done to save space. entry into the subroutine occurs with the execution of a call instruction. at that time, the processor pushes the address of the next instruction in memory following the call instruction onto the stack (allocated space in memory). when the processor encounters a ret instruction (within or at the end of the subroutine), the branch logic pops the address from the stack and begins fetching from that location. to avoid the latency of main memory accesses during call and ret operations, the return address stack caches the pushed addresses. branch execution unit the branch execution unit enables efficient speculative execution. this unit gives the processor the ability to execute instructions beyond conditional branches before knowing whether the branch prediction was correct. the amd-k6 processor does not permanently update the x86 registers or memory locations until all speculatively executed conditional branch instructions are resolved. when a prediction is incorrect, the processor backs out to the point of the mispredicted branch instruction and restores all registers. the amd-k6 can support up to seven outstanding branches.
chapter 3 software environment 21 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 3 software environment this chapter provides a general overview of the amd-k6 processors x86 software environment and briefly describes the data types, registers, operating modes, interrupts, and instructions supported by the amd-k6 architecture and design implementation. 3.1 registers the amd-k6 processor contains all the registers defined by the x86 architecture, including general-purpose, segment, floating-point, mmx, eflags, control, task, debug, test, and descriptor/memory-management registers. in addition, this chapter provides information on the amd-k6 model-specific registers (msrs). note: areas of the register designated as reserved should not be modified by software. general-purpose registers the eight 32-bit x86 general-purpose registers are used to hold integer data or memory pointers used by instructions. table 2 contains a list of the general-purpose registers and the functions for which they are used. in order to support byte and word operations, eax, ebx, ecx, and edx can also be used as 8-bit and 16-bit registers. the shorter registers are overlaid on the longer ones. for example, the name of the 16-bit version of eax is ax (low 16 bits of eax) and the 8-bit names for ax are ah (high order bits) and table 2. general-purpose registers register function eax commonly used as an accumulator ebx commonly used as a pointer ecx commonly used for counting in loop operations edx commonly used to hold i/o information and to pass parameters edi commonly used as a destination pointer by the es segment esi commonly used as a source pointer by the ds segment esp used to point to the stack segment ebp used to point to data within the stack segment
22 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information al (low order bits). the same naming convention applies to ebx, ecx, and edx. edi, esi, esp, and ebp can be used as smaller 16-bit registers called di, si, sp, and bp respectively, but these registers do not have 8-bit versions. figure 6 shows the eax register with its name components, and table 3 lists the dword (32 bits) general-purpose registers and their corresponding word (16 bits) and byte (8 bits) versions. figure 6. eax register with 16-bit and 8-bit name components 87 0 15 16 31 eax ax ah al table 3. general-purpose register dword, word, and byte names 32-bit name (dword) 16-bit name (word) 8-bit name (high-order bits) 8-bit name (low-order bits) eax ax ah al ebx bx bh bl ecx cx ch cl edx dx dh dl edi di CC esi si C C esp sp C C ebp bp C C
chapter 3 software environment 23 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information integer data types four types of data are used in general-purpose registersbyte, word, doubleword, and quadword integers. figure 7 shows the format of the integer data registers. figure 7. integer data types 15 0 31 0 precision 32 bits precision 16 bits word integer doubleword integer 70 precision 8 bits byte integer 63 0 precision 64 bits quadword integer
24 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information segment registers the six 16-bit segment registers are used as pointers to areas (segments) of memory. table 4 lists the segment registers and their functions. figure 8 shows the format for all six segment registers. figure 8. segment register segment usage the operating system determines the type of memory model that is implemented. the segment register usage is determined by the operating systems memory model. in a real mode memory model the segment register points to the base address in memory. in a protected mode memory model the segment register is called a selector and it selects a segment descriptor in a descriptor table. this descriptor contains a pointer to the base of the segment, the limit of the segment, and various protection attributes. for more information on descriptor formats, see descriptors and gates on page 45. figure 9 on page 25 shows segment usage for real mode and protected mode memory models. table 4. segment registers segment register segment register function cs code segment, where instructions are located ds data segment, where data is located es data segment, where data is located fs data segment, where data is located gs data segment, where data is located ss stack segment 0 15
chapter 3 software environment 25 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 9. segment usage instruction pointer the instruction pointer (eip or ip) is used in conjunction with the code segment register (cs). the instruction pointer is either a 32-bit register (eip) or a 16-bit register (ip) that keeps track of where the next instruction resides within memory. this register cannot be directly manipulated, but can be altered by modifying return pointers when a jmp or call instruction is used. floating-point registers the floating-point execution unit in the amd-k6 processor is designed to perform mathematical operations on non-integer numbers. this floating-point unit conforms to the ieee 754 and 854 standards and uses several registers to meet these standardseight numeric floating-point registers, a status word register, a control word register, and a tag word register. segment register real mode memory model segment selector physical memory protected mode memory model base descriptor table physical memory segment base base limit base limit segment base
26 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information the eight floating-point registers are 80 bits wide and labeled fpr0Cfpr7. figure 10 shows the format of these floating-point registers. see floating-point register data types on page 28 for information on allowable floating-point data types. figure 10. floating-point register the 16-bit fpu status word register contains information about the state of the floating-point unit. figure 11 shows the format of this register. figure 11. fpu status word register 64 63 0 78 79 sign exponent significand 9876543210 10 11 12 13 14 15 p e o e e s c 0 c 1 i e z e u e s f tosp c 3 b c 2 d e symbol description bits b fpu busy 15 c3 condition code 14 tosp top of stack pointer 13 C11 c2 condition code 10 c1 condition code 9 c0 condition code 8 es error summary status 7 sf stack fault 6 exception flags pe precision error 5 ue underflow error 4 oe overflow error 3 ze zero divide error 2 de denormalized operation error 1 ie invalid operation error 0 tosp information 000 = fpr0 111 = f p r7
chapter 3 software environment 27 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information the fpu control word register allows a programmer to manage the fpu processing options. figure 12 shows the format of this register. figure 12. fpu control word register the fpu tag word register contains information about the registers in the register stack. figure 13 shows the format of this register. figure 13. fpu tag word register symbol description bits y infinity bit (80287 compatibility) 12 rc rounding control 11C10 pc precision control 9C8 exception masks pm precision 5 um underflow 4 om overflow 3 zm zero divide 2 dm denormalized operation 1 im invalid operation 0 9876543210 10 11 12 13 14 15 p m o m p c r c i m z m u m d m rounding control information 00b = round to the nearest or even number 01b = round down toward negative infinity 10b = round up toward positive infinity 11b = truncate toward zero reserved y precision c ontrol information 00b = 24 bits single precision real 01b = reserved 10b = 53 bits double precision real 11b = 64 bits extended precision real 9876543210 10 11 12 13 14 15 tag (fpr6 tag (fpr7 tag (fpr4 tag (fpr5 tag (fpr2 tag (fpr3 tag (fpr0 tag (fpr1 tag values 00 = valid 01 = zero 10 = special 11 = empty
28 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information floating-point register data types floating-point registers use four different types of data packed decimal, single precision real, double precision real, and extended precision real. figures 14 and 15 show the formats for these registers. figure 14. packed decimal data type figure 15. precision real data types 0 79 precision 18 digits, 72 bits used, 4-bits/digit 71 s ignore or zero description bits ignored on load, zeros on store 78-72 sign bit 79 78 72 0 63 double precision real 31 0 single precision real 0 79 22 s biased exponent 78 23 s biased exponent 63 64 51 52 biased exponent s significand significand significand 30 62 extended precision real s = sign bit s = sign bit s = sign bit i 62 i = integer bit
chapter 3 software environment 29 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information mmx? registers the amd-k6 processor implements eight 64-bit mmx registers and three packed data types for use by multimedia software. these registers are mapped on the floating-point registers. the mmx instructions refer to these registers as mm0 to mm7. figures 16 and 17 show the format of these registers and data types. see amd-k6 ? processor multimedia technology , order# 20726 for more information. figure 16. mmx? registers 63 0 mm0 mm7 mm1 mm6 mm5 mm2 mm3 mm4
30 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 17. mmx? data types 63 0 packed bytes 63 0 packed words 63 0 packed doublewords 32 31 48 47 32 31 16 15 56 55 48 47 40 39 32 31 24 23 16 15 8 7
chapter 3 software environment 31 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information eflags register the eflags register provides for three different types of flagssystem, control, and status. the system flags provide operating system controls, the control flag provides directional information for string operations, and the status flags provide information resulting from logical and arithmetic operations. figure 18 shows the format of this register. figure 18. eflags registers 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 i o p l 31 30 29 28 27 26 25 24 23 22 a f p f z f s f i f d f t f o f n t r f v m a c v i f v i p i d c f reserved symbol description bits id id flag 21 vip virtual interrupt pending 20 vif virtual interrupt flag 19 ac alignment check 18 vm virtual-8086 mode 17 rf resume flag 16 nt nested task 14 iopl i/o privilege level 13C12 of overflow flag 11 df direction flag 10 if interrupt flag 9 tf trap flag 8 sf sign flag 7 zf zero flag 6 af auxiliary flag 4 pf parity flag 2 cf carry flag 0
32 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information control registers the five control registers contain system control bits and pointers. figures 19 through 23 show the formats of these registers. figure 19. control register 4 (cr4) figure 20. control register 3 (cr3) figure 21. control register 2 (cr2) 76543210 31 p s e t s d m c e v m e d e p v i reserved symbol description bi t mce machine check enable 6 pse page size extensions 4 de debugging extensions 3 tsd time stamp disable 2 pvi protected virtual interrupts 1 vme virtual-8086 mode extensions 0 p c d reserved 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 page directory base symbol description bit pcd page cache disable 4 pwt page writethrough 3 p w t 0 31 page fault linear address
chapter 3 software environment 33 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 22. control register 1 (cr1) figure 23. control register 0 (cr0) 0 31 reserved e t t s reserved 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 a m e m w p m p p e n e p g c d n w symbol description bit pg paging 31 cd cache disable 30 nw not writethrough 29 symbol description bit am alignment mask 18 wp write protect 16 ne numeric error 5 et extension type 4 ts task switched 3 em emulation 2 mp monitor co-processor 1 pe protection enabled 0
34 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information debug registers figures 24 through 27 show the 32-bit debug registers supported by the processor. figure 24. debug register dr7 symbol description bit gd general detect enabled 13 ge global exact breakpoint enabled 9 le local exact breakpoint enabled 8 g3 global exact breakpoint # 3 enabled 7 l3 local exact breakpoint # 3 enabled 6 g2 global exact breakpoint # 2 enabled 5 l2 local exact breakpoint # 2 enabled 4 g1 global exact breakpoint # 1 enabled 3 l1 local exact breakpoint # 1 enabled 2 g0 global exact breakpoint # 0 enabled 1 l0 local exact breakpoint # 0 enabled 0 9876543210 10 11 12 13 14 15 l 2 l 1 l 3 g 3 g e l e l 0 reserved g 0 g 1 l 2 g d 25 24 23 22 21 20 19 18 17 16 26 27 28 29 30 31 r/w 3 len 3 r/w 2 len 2 r/w 1 len 1 r/w 0 len 0 symbol description bits len 3 length of breakpoint #3 31C30 r/w 3 type of transaction(s) to trap 29C28 len 2 length of breakpoint #2 27C26 r/w 2 type of transaction(s) to trap 25C24 len 1 length of breakpoint #1 23C22 r/w 1 type of transaction(s) to trap 21C20 len 0 length of breakpoint #0 19C18 r/w 0 type of transaction(s) to trap 17C16
chapter 3 software environment 35 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 25. debug register dr6 figure 26. debug registers dr5 and dr4 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 b 1 b 2 b s b 0 reserved b t b d symbol description bit bt breakpoint task switch 15 bs breakpoint single step 14 bd breakpoint debug access detected 13 b3 breakpoint #3 condition detected 3 b2 breakpoint #2 condition detected 2 b1 breakpoint #1 condition detected 1 b0 breakpoint #0 condition detected 0 b 3 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr5 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr4
36 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 27. debug registers dr3, dr2, dr1, and dr0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 3 32-bit linear address dr3 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 0 32-bit linear address dr0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 2 32-bit linear address dr2 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 1 32-bit linear address dr1
chapter 3 software environment 37 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information model-specific registers (msr) the amd-k6 processor provides five msrs. the value in the ecx register selects the msr to be addressed by the rdmsr and wrmsr instructions. the values in eax and edx are used as inputs and outputs by the rdmsr and wrmsr instructions. table 5 lists the msrs and the corresponding value of the ecx register. figures 28 through 32 show the msr formats. for more information about the rdmsr and wrmsr instructions, see the amd k86? family bios and software tools development guide , order# 21062. mcar and mctr. the amd-k6 processor does not support the generation of a machine check exception. however, the processor does provide a 64-bit machine check address register (mcar), a 64-bit machine check type register (mctr), and a machine check enable (mce) bit in cr4. because the processor does not support machine check exceptions, the contents of the mcar and mctr are only affected by the wrmsr instruction and by reset being sampled asserted (where all bits in each register are reset to 0). figure 28. machine-check address register (mcar) table 5. model - specific registers (msrs) model-specific register value of ecx machine check address register (mcar) 00h machine check type register (mctr) 01h test register 12 (tr12) 0eh time stamp counter (tsc) 10h write handling control register (whcr) c000_0082h 0 63 mcar
38 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 29. machine-check type register (mctr) test register 12 (tr12). test register 12 provides a method for disabling the l1 caches. figure 30 shows the format of tr12. figure 30. test register 12 (tr12) time stamp counter. with each processor clock cycle, the processor increments the 64-bit time stamp counter (tsc) msr. figure 31 shows the format of the tsc. figure 31. time stamp counter (tsc) 54 0 63 reserved mctr reserved 4210 63 c i 3 symbol description bit ci cache inhibit bit 3 0 63 tsc
chapter 3 software environment 39 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information write handling control register (whcr). the write handling control register (whcr) is a msr that contains three fieldsthe wcde bit, write allocate enable limit (waelim) field, and the write allocate enable 15-to-16-mbyte (wae15m) bit. figure 32 shows the format of whcr. see write allocate on page 177 for more information. figure 32. write handling control register (whcr) memory management registers the amd-k6 processor controls segmented memory management with the registers listed in table 6. figure 33 on page 40 shows the formats of these registers. 710 63 reserved waelim 8 0 note : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits wcde always program to 0 8 waelim write allocate enable limit 7C1 wae15m write allocate enable 15-to-16-mbyte 0 9 table 6. memory management registers register name function global descriptor table register contains a pointer to the base of the global descriptor table interrupt descriptor table register contains a pointer to the base of the interrupt descriptor table local descriptor table register contains a pointer to the local descriptor table of the current task task register contains a pointer to the task state segment of the current task
40 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 33. memory management registers 15 0 16-bit limit 16 47 32-bit linear base address global and interrupt descriptor table registers 31 0 63 32-bit limit 32 32-bit linear base address 15 0 local descriptor table register and task register attributes 15 0 selector
chapter 3 software environment 41 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information task state segment figure 34 shows the format of the task state segment (tss). figure 34. task state segment (tss) 31 interrupt redirection bitmap (irb) (eight 32-bit locations) 0 i/o permission bitmap (iopb) (up to 8 kbytes) operating system data structure base address of iopb ldt selector 0000h 0000h 0000h 0000h 0000h 0000h 0000h gs fs ds ss cs es edi esi ebp esp ebx edx ecx eax cr3 eflags eip 0000h 0000h 0000h 0000h ss2 ss1 ss0 link (prior tss selector) esp0 esp1 esp2 tss limit from tr 64h 0 t 0000h
42 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information paging the amd-k6 processor can address up to 4 gbytes of memory. this memory can be segmented into pages. the size of these pages is determined by the operating system design and the values set up in the page directory entries (pde) and page table entries (pte). the processor can access both 4-kbyte pages and 4-mbyte pages, and the page sizes can be intermixed within a page directory. when the page size extension (pse) bit in cr4 is set, the processor translates linear addresses using either the 4-kbyte translation lookaside buffer (tlb) or the 4-mbyte tlb, depending on the state of the page size (ps) bit in the page directory entry. figures 35 and 36 show how 4-kbyte and 4-mbyte page translations work. figure 35. 4-kbyte paging mechanism linear address page directory page table 4-kbyte page frame cr3 0 11 12 21 31 22 page directory offset page table offset page offset pde pte physical address
chapter 3 software environment 43 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 36. 4-mbyte paging mechanism figures 37 through 39 show the formats of the pde and pte. these entries contain information regarding the location of pages and their status. linear address page directory 4-mbyte page frame cr3 0 21 31 22 page directory offset page offset pde physical address
44 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 37. page directory entry 4-kbyte page table (pde) figure 38. page directory entry 4-mbyte page table (pde) 876543210 31 p c d u / s w / r 9 10 11 12 a v l 0 a p w t p page table base address symbol description bits avl available to software 11C9 reserved 8 ps page size 7 reserved 6 a accessed 5 pcd page cache disable 4 pwt page writethrough 3 u/s user/supervisor 2 w/r write/read 1 p present (valid) 0 876543210 31 p c d u / s w / r 9 10 11 12 a v l 1 a p w t p physical page base address reserved 21 22 symbol description bits avl available to software 11C9 reserved 8 ps page size 7 reserved 6 a accessed 5 pcd page cache disable 4 pwt page writethrough 3 u/s user/supervisor 2 w/r write/read 1 p present (valid) 0
chapter 3 software environment 45 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 39. page table entry (pte) descriptors and gates there are various types of structures and registers in the x86 architecture that define, protect, and isolate code segments, data segments, task state segments, and gates. these structures are called descriptors. figure 40 on page 46 shows the application segment descriptor format. table 7 contains information describing the memory segment type to which the descriptor points. the application segment descriptor is used to point to either a data or code segment. figure 41 on page 47 shows the system segment descriptor format. table 8 contains information describing the type of segment or gate to which the descriptor points. the system segment descriptor is used to point to a task state segment, a call gate, or a local descriptor table. the amd-k6 processor uses gates to transfer control between executable segments with different privilege levels. figure 42 on page 48 shows the format of the gate descriptor types. table 8 contains information describing the type of segment or gate to which the descriptor points. 876543210 31 p c d u / s w / r 9 10 11 12 a v l a p w t p physical page base address symbol description bits avl available to software 11C9 reserved 8C7 d dirty 6 a accessed 5 pcd page cache disable 4 pwt page writethrough 3 u/s user/supervisor 2 w/r write/read 1 p present (valid) 0 d
46 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 40. application segment descriptor base address 15C0 segment limit 15C0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 segment limit p dpl 1 type a v l g d base address 31C24 base address 23C16 symbol description bits g granularity 23 d 32-bit/16-bit 22 avl available to software 20 p present/valid bit 15 dpl descriptor privilege level 14-13 dt descriptor type 12 type see table 7 11-8 reserved table 7. application segment types type data/code description 0 data read-only 1 read-only accessed 2 read/write 3 read/writeaccessed 4 read-onlyexpand-down 5 read-onlyexpand-down, accessed 6 read/writeexpand-down 7 read/writeexpand-down, accessed 8 code execute-only 9 execute-onlyaccessed a execute/read b execute/readaccessed c execute-onlyconforming d execute-onlyconforming, accessed e execute/read-onlyconforming f execute/read-onlyconforming, accessed
chapter 3 software environment 47 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 41. system segment descriptor base address 15C0 segment limit 15C0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 segment limit p dpl 0 type a v l g x base address 31C24 base address 23C16 symbol description bits g granularity 23 x not needed 22 avl availability to software 20 p present/valid bit 15 dpl descriptor privilege level 14-13 dt descriptor type 12 type see table 8 11-8 reserved table 8. system segment and gate types type description 0 reserved 1 available 16-bit tss 2ldt 3 busy 16-bit tss 4 16-bit call gate 5 task gate 6 16-bit interrupt gate 7 16-bit trap gate 8 reserved 9 available 32-bit tss a reserved b busy 32-bit tss c 32-bit call gate d reserved e 32-bit interrupt gate f 32-bit trap gate
48 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 42. gate descriptor exceptions and interrupts table 9 summarizes the exceptions and interrupts. dpl 0 type offset 31C16 p segment selector offset 15C0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 symbol description bits p present/valid bit 15 dpl descriptor privilege level 14-13 dt descriptor type 12 type see table 8 11-8 reserved table 9. summary of exceptions and interrupts interrupt number interrupt type cause 0 divide by zero error div, idiv 1 debug debug trap or fault 2 non-maskable interrupt nmi signal sampled asserted 3 breakpoint int 3 4 overflow into 5 bounds check bound 6 invalid opcode invalid instruction 7 device not available esc and wait 8 double fault fault occurs while handling a fault 9 reserved - interrupt 13 10 invalid tss task switch to an invalid segment 11 segment not present instruction loads a segment and present bit is 0 (invalid segment) 12 stack segment stack operation causes limit violation or present bit is 0 13 general protection segment related or miscellaneous invalid actions 14 page fault page protection violation or a reference to missing page 16 floating-point error arithmetic error generated by floating-point instruction 17 alignment check data reference to an unaligned operand. (the ac flag and the am bit of cr0 are set to 1.) 0-255 software interrupt int n
chapter 3 software environment 49 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 3.2 instructions supported by the amd-k6 ? processor this section documents all of the x86 instructions supported by the amd-k6 processor. the following tables show the instruction mnemonic, opcode, modr/m byte, decode type, and risc86 operation(s) for each instruction. tables 10 through 12 define the integer, floating-point, and mmx instructions, respectively. the first column in these tables indicates the instruction mnemonic and operand types with the following notations: n reg8 byte integer register defined by instruction byte(s) or bits 5, 4, and 3 of the modr/m byte n mreg8 byte integer register defined by bits 2, 1, and 0 of the modr/m byte n reg16/32 word and doubleword integer register defined by instruction byte(s) or bits 5, 4, and 3 of the modr/m byte n mreg16/32 word and doubleword integer register defined by bits 2, 1, and 0 of the modr/m byte n mem8 byte integer value in memory n mem16/32 word or doubleword integer value in memory n mem32/48 doubleword or 48-bit integer value in memory n mem48 48-bit integer value in memory n mem64 64-bit value in memory n imm8 8-bit immediate value n imm16/32 16-bit or 32-bit immediate value n disp8 8-bit displacement value n disp16/32 16-bit or 32-bit displacement value n disp32/48 doubleword or 48-bit displacement value n exx register width depending on the operand size n mem32real 32-bit floating-point value in memory n mem64real 64-bit floating-point value in memory n mem80real 80-bit floating-point value in memory n mmreg mmx register n mmreg1 mmx register defined by bits 5, 4, and 3 of the modr/m byte n mmreg2 mmx register defined by bits 2, 1, and 0 of the modr/m byte
50 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information the second and third columns list all applicable opcode bytes. the fourth column lists the modr/m byte when used by the instruction. the modr/m byte defines the instruction as a register or memory form. if modr/m bits 7 and 6 are documented as mm (memory form), mm can only be 10b, 01b or 00b. the fifth column lists the type of instruction decodeshort, long, and vector. the amd-k6 decode logic can process two short, one long, or one vector decode per clock. the sixth column lists the type of risc86 operation(s) required for the instruction. the operation types and corresponding execution units are as follows: n load, fload, mload load unit n store, fstore, mstore store unit n alu either of the integer execution units n alux integer x execution unit only n branch branch condition unit n float floating-point execution unit n meu multimedia execution unit for mmx software n limm load immediate, instruction control unit table 10. integer instructions instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes aaa 37h vector aad d5h 0ah vector aam d4h 0ah vector aas 3fh vector adc mreg8, reg8 10h 11-xxx-xxx short alux adc mem8, reg8 10h mm-xxx-xxx long load, alux, store adc mreg16/32, reg16/32 11h 11-xxx-xxx short alu adc mem16/32, reg16/32 11h mm-xxx-xxx long load, alu, store adc reg8, mreg8 12h 11-xxx-xxx short alux adc reg8, mem8 12h mm-xxx-xxx short load, alux adc reg16/32, mreg16/32 13h 11-xxx-xxx short alu adc reg16/32, mem16/32 13h mm-xxx-xxx short load, alu adc al, imm8 14h xx-xxx-xxx short alux
chapter 3 software environment 51 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information adc eax, imm16/32 15h xx-xxx-xxx short alu adc mreg8, imm8 80h 11-010-xxx short alux adc mem8, imm8 80h mm-010-xxx long load, alux, store adc mreg16/32, imm16/32 81h 11-010-xxx short alu adc mem16/32, imm16/32 81h mm-010-xxx long load, alu, store adc mreg16/32, imm8 (signed ext.) 83h 11-010-xxx short alux adc mem16/32, imm8 (signed ext.) 83h mm-010-xxx long load, alux, store add mreg8, reg8 00h 11-xxx-xxx short alux add mem8, reg8 00h mm-xxx-xxx long load, alux, store add mreg16/32, reg16/32 01h 11-xxx-xxx short alu add mem16/32, reg16/32 01h mm-xxx-xxx long load, alu, store add reg8, mreg8 02h 11-xxx-xxx short alux add reg8, mem8 02h mm-xxx-xxx short load, alux add reg16/32, mreg16/32 03h 11-xxx-xxx short alu add reg16/32, mem16/32 03h mm-xxx-xxx short load, alu add al, imm8 04h xx-xxx-xxx short alux add eax, imm16/32 05h xx-xxx-xxx short alu add mreg8, imm8 80h 11-000-xxx short alux add mem8, imm8 80h mm-000-xxx long load, alux, store add mreg16/32, imm16/32 81h 11-000-xxx short alu add mem16/32, imm16/32 81h mm-000-xxx long load, alu, store add mreg16/32, imm8 (signed ext.) 83h 11-000-xxx short alux add mem16/32, imm8 (signed ext.) 83h mm-000-xxx long load, alux, store and mreg8, reg8 20h 11-xxx-xxx short alux and mem8, reg8 20h mm-xxx-xxx long load, alux, store and mreg16/32, reg16/32 21h 11-xxx-xxx short alu and mem16/32, reg16/32 21h mm-xxx-xxx long load, alu, store and reg8, mreg8 22h 11-xxx-xxx short alux and reg8, mem8 22h mm-xxx-xxx short load, alux and reg16/32, mreg16/32 23h 11-xxx-xxx short alu and reg16/32, mem16/32 23h mm-xxx-xxx short load, alu and al, imm8 24h xx-xxx-xxx short alux and eax, imm16/32 25h xx-xxx-xxx short alu table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
52 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information and mreg8, imm8 80h 11-100-xxx short alux and mem8, imm8 80h mm-100-xxx long load, alux, store and mreg16/32, imm16/32 81h 11-100-xxx short alu and mem16/32, imm16/32 81h mm-100-xxx long load, alu, store and mreg16/32, imm8 (signed ext.) 83h 11-100-xxx short alux and mem16/32, imm8 (signed ext.) 83h mm-100-xxx long load, alux, store arpl mreg16, reg16 63h 11-xxx-xxx vector arpl mem16, reg16 63h mm-xxx-xxx vector bound 62h xx-xxx-xxx vector bsf reg16/32, mreg16/32 0fh bch 11-xxx-xxx vector bsf reg16/32, mem16/32 0fh bch mm-xxx-xxx vector bsr reg16/32, mreg16/32 0fh bdh 11-xxx-xxx vector bsr reg16/32, mem16/32 0fh bdh mm-xxx-xxx vector bswap eax 0fh c8h long alu bswap ecx 0fh c9h long alu bswap edx 0fh cah long alu bswap ebx 0fh cbh long alu bswap esp 0fh cch long alu bswap ebp 0fh cdh long alu bswap esi 0fh ceh long alu bswap edi 0fh cfh long alu bt mreg16/32, reg16/32 0fh a3h 11-xxx-xxx vector bt mem16/32, reg16/32 0fh a3h mm-xxx-xxx vector bt mreg16/32, imm8 0fh bah 11-100-xxx vector bt mem16/32, imm8 0fh bah mm-100-xxx vector btc mreg16/32, reg16/32 0fh bbh 11-xxx-xxx vector btc mem16/32, reg16/32 0fh bbh mm-xxx-xxx vector btc mreg16/32, imm8 0fh bah 11-111-xxx vector btc mem16/32, imm8 0fh bah mm-111-xxx vector btr mreg16/32, reg16/32 0fh b3h 11-xxx-xxx vector btr mem16/32, reg16/32 0fh b3h mm-xxx-xxx vector btr mreg16/32, imm8 0fh bah 11-110-xxx vector btr mem16/32, imm8 0fh bah mm-110-xxx vector table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
chapter 3 software environment 53 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information bts mreg16/32, reg16/32 0fh abh 11-xxx-xxx vector bts mem16/32, reg16/32 0fh abh mm-xxx-xxx vector bts mreg16/32, imm8 0fh bah 11-101-xxx vector bts mem16/32, imm8 0fh bah mm-101-xxx vector call full pointer 9ah vector call near imm16/32 e8h short store call mem16:16/32 ffh 11-011-xxx vector call near mreg32 (indirect) ffh 11-010-xxx vector call near mem32 (indirect) ffh mm-010-xxx vector cbw/cwde eax 98h vector clc f8h vector cld fch vector cli fah vector clts 0fh 06h vector cmc f5h vector cmp mreg8, reg8 38h 11-xxx-xxx short alux cmp mem8, reg8 38h mm-xxx-xxx short load, alux cmp mreg16/32, reg16/32 39h 11-xxx-xxx short alu cmp mem16/32, reg16/32 39h mm-xxx-xxx short load, alu cmp reg8, mreg8 3ah 11-xxx-xxx short alux cmp reg8, mem8 3ah mm-xxx-xxx short load, alux cmp reg16/32, mreg16/32 3bh 11-xxx-xxx short alu cmp reg16/32, mem16/32 3bh mm-xxx-xxx short load, alu cmp al, imm8 3ch xx-xxx-xxx short alux cmp eax, imm16/32 3dh xx-xxx-xxx short alu cmp mreg8, imm8 80h 11-111-xxx short alux cmp mem8, imm8 80h mm-111-xxx short load, alux cmp mreg16/32, imm16/32 81h 11-111-xxx short alu cmp mem16/32, imm16/32 81h mm-111-xxx short load, alu cmp mreg16/32, imm8 (signed ext.) 83h 11-111-xxx long load, alu cmp mem16/32, imm8 (signed ext.) 83h mm-111-xxx long load, alu cmpsb mem8,mem8 a6h vector cmpsw mem16, mem32 a7h vector table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
54 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information cmpsd mem32, mem32 a7h vector cmpxchg mreg8, reg8 0fh b0h 11-xxx-xxx vector cmpxchg mem8, reg8 0fh b0h mm-xxx-xxx vector cmpxchg mreg16/32, reg16/32 0fh b1h 11-xxx-xxx vector cmpxchg mem16/32, reg16/32 0fh b1h mm-xxx-xxx vector cmpxch8b edx:eax 0fh c7h 11-xxx-xxx vector cmpxch8b mem64 0fh c7h mm-xxx-xxx vector cpuid 0fh a2h vector cwd/cdq edx, eax 99h vector daa 27h vector das 2fh vector dec eax 48h short alu dec ecx 49h short alu dec edx 4ah short alu dec ebx 4bh short alu dec esp 4ch short alu dec ebp 4dh short alu dec esi 4eh short alu dec edi 4fh short alu dec mreg8 feh 11-001-xxx vector dec mem8 feh mm-001-xxx long load, alux, store dec mreg16/32 ffh 11-001-xxx vector dec mem16/32 ffh mm-001-xxx long load, alu, store div al, mreg8 f6h 11-110-xxx vector div al, mem8 f6h mm-110-xxx vector div eax, mreg16/32 f7h 11-110-xxx vector div eax, mem16/32 f7h mm-110-xxx vector idiv mreg8 f6h 11-111-xxx vector idiv mem8 f6h mm-111-xxx vector idiv eax, mreg16/32 f7h 11-111-xxx vector idiv eax, mem16/32 f7h mm-111-xxx vector imul reg16/32, imm16/32 69h 11-xxx-xxx vector imul reg16/32, mreg16/32, imm16/32 69h 11-xxx-xxx vector table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
chapter 3 software environment 55 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information imul reg16/32, mem16/32, imm16/32 69h mm-xxx-xxx vector imul reg16/32, imm8 (sign extended) 6bh 11-xxx-xxx vector imul reg16/32, mreg16/32, imm8 (signed) 6bh 11-xxx-xxx vector imul reg16/32, mem16/32, imm8 (signed) 6bh mm-xxx-xxx vector imul ax, al, mreg8 f6h 11-101-xxx vector imul ax, al, mem8 f6h mm-101-xxx vector imul edx:eax, eax, mreg16/32 f7h 11-101-xxx vector imul edx:eax, eax, mem16/32 f7h mm-101-xxx vector imul reg16/32, mreg16/32 0fh afh 11-xxx-xxx vector imul reg16/32, mem16/32 0fh afh mm-xxx-xxx vector inc eax 40h short alu inc ecx 41h short alu inc edx 42h short alu inc ebx 43h short alu inc esp 44h short alu inc ebp 45h short alu inc esi 46h short alu inc edi 47h short alu inc mreg8 feh 11-000-xxx vector inc mem8 feh mm-000-xxx long load, alux, store inc mreg16/32 ffh 11-000-xxx vector inc mem16/32 ffh mm-000-xxx long load, alu, store invd 0fh 08h vector invlpg 0fh 01h mm-111-xxx vector jo short disp8 70h short branch jb/jnae short disp8 71h short branch jno short disp8 71h short branch jnb/jae short disp8 73h short branch jz/je short disp8 74h short branch jnz/jne short disp8 75h short branch jbe/jna short disp8 76h short branch table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
56 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information jnbe/ja short disp8 77h short branch js short disp8 78h short branch jns short disp8 79h short branch jp/jpe short disp8 7ah short branch jnp/jpo short disp8 7bh short branch jl/jnge short disp8 7ch short branch jnl/jge short disp8 7dh short branch jle/jng short disp8 7eh short branch jnle/jg short disp8 7fh short branch jcxz/jec short disp8 e3h vector jo near disp16/32 0fh 80h short branch jno near disp16/32 0fh 81h short branch jb/jnae near disp16/32 0fh 82h short branch jnb/jae near disp16/32 0fh 83h short branch jz/je near disp16/32 0fh 84h short branch jnz/jne near disp16/32 0fh 85h short branch jbe/jna near disp16/32 0fh 86h short branch jnbe/ja near disp16/32 0fh 87h short branch js near disp16/32 0fh 88h short branch jns near disp16/32 0fh 89h short branch jp/jpe near disp16/32 0fh 8ah short branch jnp/jpo near disp16/32 0fh 8bh short branch jl/jnge near disp16/32 0fh 8ch short branch jnl/jge near disp16/32 0fh 8dh short branch jle/jng near disp16/32 0fh 8eh short branch jnle/jg near disp16/32 0fh 8fh short branch jmp near disp16/32 (direct) e9h short branch jmp far disp32/48 (direct) eah vector jmp disp8 (short) ebh short branch jmp far mreg32 (indirect) efh 11-101-xxx vector jmp far mem32 (indirect) efh mm-101-xxx vector jmp near mreg16/32 (indirect) ffh 11-100-xxx vector jmp near mem16/32 (indirect) ffh mm-100-xxx vector table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
chapter 3 software environment 57 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information lahf 9fh vector lar reg16/32, mreg16/32 0fh 02h 11-xxx-xxx vector lar reg16/32, mem16/32 0fh 02h mm-xxx-xxx vector lds reg16/32, mem32/48 c5h mm-xxx-xxx vector lea reg16/32, mem16/32 8dh mm-xxx-xxx short load, alu leave c9h long load, alu, alu les reg16/32, mem32/48 c4h mm-xxx-xxx vector lfs reg16/32, mem32/48 0fh b4h vector lgdt mem48 0fh 01h mm-010-xxx vector lgs reg16/32, mem32/48 0fh b5h vector lidt mem48 0fh 01h mm-011-xxx vector lldt mreg16 0fh 00h 11-010-xxx vector lldt mem16 0fh 00h mm-010-xxx vector lmsw mreg16 0fh 01h 11-100-xxx vector lmsw mem16 0fh 01h mm-100-xxx vector lodsb al, mem8 ach long load, alux lodsw ax, mem16 adh long load, alu lodsd eax, mem32 adh long load, alu loop disp8 e2h short alu, branch loope/loopz disp8 e1h vector loopne/loopnz disp8 e0h vector lsl reg16/32, mreg16/32 0fh 03h 11-xxx-xxx vector lsl reg16/32, mem16/32 0fh 03h mm-xxx-xxx vector lss reg16/32, mem32/48 0fh b2h mm-xxx-xxx vector ltr mreg16 0fh 00h 11-011-xxx vector ltr mem16 0fh 00h mm-011-xxx vector mov mreg8, reg8 88h 11-xxx-xxx short alux mov mem8, reg8 88h mm-xxx-xxx short store mov mreg16/32, reg16/32 89h 11-xxx-xxx short alu mov mem16/32, reg16/32 89h mm-xxx-xxx short store mov reg8, mreg8 8ah 11-xxx-xxx short alux mov reg8, mem8 8ah mm-xxx-xxx short load mov reg16/32, mreg16/32 8bh 11-xxx-xxx short alu table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
58 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information mov reg16/32, mem16/32 8bh mm-xxx-xxx short load mov mreg16, segment reg 8ch 11-xxx-xxx long load mov mem16, segment reg 8ch mm-xxx-xxx vector mov segment reg, mreg16 8eh 11-xxx-xxx vector mov segment reg, mem16 8eh mm-xxx-xxx vector mov al, mem8 a0h short load mov eax, mem16/32 a1h short load mov mem8, al a2h short store mov mem16/32, eax a3h short store mov al, imm8 b0h short limm mov cl, imm8 b1h short limm mov dl, imm8 b2h short limm mov bl, imm8 b3h short limm mov ah, imm8 b4h short limm mov ch, imm8 b5h short limm mov dh, imm8 b6h short limm mov bh, imm8 b7h short limm mov eax, imm16/32 b8h short limm mov ecx, imm16/32 b9h short limm mov edx, imm16/32 bah short limm mov ebx, imm16/32 bbh short limm mov esp, imm16/32 bch short limm mov ebp, imm16/32 bdh short limm mov esi, imm16/32 beh short limm mov edi, imm16/32 bfh short limm mov mreg8, imm8 c6h 11-000-xxx short limm mov mem8, imm8 c6h mm-000-xxx long store mov reg16/32, imm16/32 c7h 11-000-xxx short limm mov mem16/32, imm16/32 c7h mm-000-xxx long store movsb mem8,mem8 a4h long load, store, alux, alux movsd mem16, mem16 a5h long load, store, alu, alu movsw mem32, mem32 a5h long load, store, alu, alu movsx reg16/32, mreg8 0fh beh 11-xxx-xxx short alu table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
chapter 3 software environment 59 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information movsx reg16/32, mem8 0fh beh mm-xxx-xxx short load, alu movsx reg32, mreg16 0fh bfh 11-xxx-xxx short alu movsx reg32, mem16 0fh bfh mm-xxx-xxx short load, alu movzx reg16/32, mreg8 0fh b6h 11-xxx-xxx short alu movzx reg16/32, mem8 0fh b6h mm-xxx-xxx short load, alu movzx reg32, mreg16 0fh b7h 11-xxx-xxx short alu movzx reg32, mem16 0fh b7h mm-xxx-xxx short load, alu mul al, mreg8 f6h 11-100-xxx vector mul al, mem8 f6h mm-100-xxx vector mul eax, mreg16/32 f7h 11-100-xxx vector mul eax, mem16/32 f7h mm-100-xxx vector neg mreg8 f6h 11-011-xxx short alux neg mem8 f6h mm-011-xxx vector neg mreg16/32 f7h 11-011-xxx short alu neg mem16/32 f7h mm-011-xxx vector nop (xchg ax, ax) 90h short limm not mreg8 f6h 11-010-xxx short alux not mem8 f6h mm-010-xxx vector not mreg16/32 f7h 11-010-xxx short alu not mem16/32 f7h mm-010-xxx vector or mreg8, reg8 08h 11-xxx-xxx short alux or mem8, reg8 08h mm-xxx-xxx long load, alux, store or mreg16/32, reg16/32 09h 11-xxx-xxx short alu or mem16/32, reg16/32 09h mm-xxx-xxx long load, alu, store or reg8, mreg8 0ah 11-xxx-xxx short alux or reg8, mem8 0ah mm-xxx-xxx short load, alux or reg16/32, mreg16/32 0bh 11-xxx-xxx short alu or reg16/32, mem16/32 0bh mm-xxx-xxx short load, alu or al, imm8 0ch xx-xxx-xxx short alux or eax, imm16/32 0dh xx-xxx-xxx short alu or mreg8, imm8 80h 11-001-xxx short alux or mem8, imm8 80h mm-001-xxx long load, alux, store or mreg16/32, imm16/32 81h 11-001-xxx short alu table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
60 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information or mem16/32, imm16/32 81h mm-001-xxx long load, alu, store or mreg16/32, imm8 (signed ext.) 83h 11-001-xxx short alux or mem16/32, imm8 (signed ext.) 83h mm-001-xxx long load, alux, store pop es 07h vector pop ss 17h vector pop ds 1fh vector pop fs 0fh a1h vector pop gs 0fh a9h vector pop eax 58h short load, alu pop ecx 59h short load, alu pop edx 5ah short load, alu pop ebx 5bh short load, alu pop esp 5ch short load, alu pop ebp 5dh short load, alu pop esi 5eh short load, alu pop edi 5fh short load, alu pop mreg 8fh 11-000-xxx short load, alu pop mem 8fh mm-000-xxx long load, store, alu popa/popad 61h vector popf/popfd 9dh vector push es 06h long load, store push cs 0eh vector push fs 0fh a0h vector push gs 0fh a8h vector push ss 16h vector push ds 1eh long load, store push eax 50h short store push ecx 51h short store push edx 52h short store push ebx 53h short store push esp 54h short store push ebp 55h short store push esi 56h short store table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
chapter 3 software environment 61 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information push edi 57h short store push imm8 6ah long store push imm16/32 68h long store push mreg16/32 ffh 11-110-xxx vector push mem16/32 ffh mm-110-xxx long load, store pusha/pushad 60h vector pushf/pushfd 9ch vector rcl mreg8, imm8 c0h 11-010-xxx vector rcl mem8, imm8 c0h mm-010-xxx vector rcl mreg16/32, imm8 c1h 11-010-xxx vector rcl mem16/32, imm8 c1h mm-010-xxx vector rcl mreg8, 1 d0h 11-010-xxx vector rcl mem8, 1 d0h mm-010-xxx vector rcl mreg16/32, 1 d1h 11-010-xxx vector rcl mem16/32, 1 d1h mm-010-xxx vector rcl mreg8, cl d2h 11-010-xxx vector rcl mem8, cl d2h mm-010-xxx vector rcl mreg16/32, cl d3h 11-010-xxx vector rcl mem16/32, cl d3h mm-010-xxx vector rcr mreg8, imm8 c0h 11-011-xxx vector rcr mem8, imm8 c0h mm-011-xxx vector rcr mreg16/32, imm8 c1h 11-011-xxx vector rcr mem16/32, imm8 c1h mm-011-xxx vector rcr mreg8, 1 d0h 11-011-xxx vector rcr mem8, 1 d0h mm-011-xxx vector rcr mreg16/32, 1 d1h 11-011-xxx vector rcr mem16/32, 1 d1h mm-011-xxx vector rcr mreg8, cl d2h 11-011-xxx vector rcr mem8, cl d2h mm-011-xxx vector rcr mreg16/32, cl d3h 11-011-xxx vector rcr mem16/32, cl d3h mm-011-xxx vector ret near imm16 c2h vector ret near c3h vector table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
62 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information ret far imm16 cah vector ret far cbh vector rol mreg8, imm8 c0h 11-000-xxx vector rol mem8, imm8 c0h mm-000-xxx vector rol mreg16/32, imm8 c1h 11-000-xxx vector rol mem16/32, imm8 c1h mm-000-xxx vector rol mreg8, 1 d0h 11-000-xxx vector rol mem8, 1 d0h mm-000-xxx vector rol mreg16/32, 1 d1h 11-000-xxx vector rol mem16/32, 1 d1h mm-000-xxx vector rol mreg8, cl d2h 11-000-xxx vector rol mem8, cl d2h mm-000-xxx vector rol mreg16/32, cl d3h 11-000-xxx vector rol mem16/32, cl d3h mm-000-xxx vector ror mreg8, imm8 c0h 11-001-xxx vector ror mem8, imm8 c0h mm-001-xxx vector ror mreg16/32, imm8 c1h 11-001-xxx vector ror mem16/32, imm8 c1h mm-001-xxx vector ror mreg8, 1 d0h 11-001-xxx vector ror mem8, 1 d0h mm-001-xxx vector ror mreg16/32, 1 d1h 11-001-xxx vector ror mem16/32, 1 d1h mm-001-xxx vector ror mreg8, cl d2h 11-001-xxx vector ror mem8, cl d2h mm-001-xxx vector ror mreg16/32, cl d3h 11-001-xxx vector ror mem16/32, cl d3h mm-001-xxx vector sahf 9eh vector sar mreg8, imm8 c0h 11-111-xxx short alux sar mem8, imm8 c0h mm-111-xxx vector sar mreg16/32, imm8 c1h 11-111-xxx short alu sar mem16/32, imm8 c1h mm-111-xxx vector sar mreg8, 1 d0h 11-111-xxx short alux sar mem8, 1 d0h mm-111-xxx vector table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
chapter 3 software environment 63 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information sar mreg16/32, 1 d1h 11-111-xxx short alu sar mem16/32, 1 d1h mm-111-xxx vector sar mreg8, cl d2h 11-111-xxx short alux sar mem8, cl d2h mm-111-xxx vector sar mreg16/32, cl d3h 11-111-xxx short alu sar mem16/32, cl d3h mm-111-xxx vector sbb mreg8, reg8 18h 11-xxx-xxx short alux sbb mem8, reg8 18h mm-xxx-xxx long load, alux, store sbb mreg16/32, reg16/32 19h 11-xxx-xxx short alu sbb mem16/32, reg16/32 19h mm-xxx-xxx long load, alu, store sbb reg8, mreg8 1ah 11-xxx-xxx short alux sbb reg8, mem8 1ah mm-xxx-xxx short load, alux sbb reg16/32, mreg16/32 1bh 11-xxx-xxx short alu sbb reg16/32, mem16/32 1bh mm-xxx-xxx short load, alu sbb al, imm8 1ch xx-xxx-xxx short alux sbb eax, imm16/32 1dh xx-xxx-xxx short alu sbb mreg8, imm8 80h 11-011-xxx short alux sbb mem8, imm8 80h mm-011-xxx long load, alux, store sbb mreg16/32, imm16/32 81h 11-011-xxx short alu sbb mem16/32, imm16/32 81h mm-011-xxx long load, alu, store sbb mreg8, imm8 (signed ext.) 83h 11-011-xxx short alux sbb mem8, imm8 (signed ext.) 83h mm-011-xxx long load, alux, store scasb al, mem8 aeh vector scasw ax, mem16 afh vector scasd eax, mem32 afh vector seto mreg8 0fh 90h 11-xxx-xxx vector seto mem8 0fh 90h mm-xxx-xxx vector setno mreg8 0fh 91h 11-xxx-xxx vector setno mem8 0fh 91h mm-xxx-xxx vector setb/setnae mreg8 0fh 92h 11-xxx-xxx vector setb/setnae mem8 0fh 92h mm-xxx-xxx vector setnb/setae mreg8 0fh 93h 11-xxx-xxx vector setnb/setae mem8 0fh 93h mm-xxx-xxx vector table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
64 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information setz/sete mreg8 0fh 94h 11-xxx-xxx vector setz/sete mem8 0fh 94h mm-xxx-xxx vector setnz/setne mreg8 0fh 95h 11-xxx-xxx vector setnz/setne mem8 0fh 95h mm-xxx-xxx vector setbe/setna mreg8 0fh 96h 11-xxx-xxx vector setbe/setna mem8 0fh 96h mm-xxx-xxx vector setnbe/seta mreg8 0fh 97h 11-xxx-xxx vector setnbe/seta mem8 0fh 97h mm-xxx-xxx vector sets mreg8 0fh 98h 11-xxx-xxx vector sets mem8 0fh 98h mm-xxx-xxx vector setns mreg8 0fh 99h 11-xxx-xxx vector setns mem8 0fh 99h mm-xxx-xxx vector setp/setpe mreg8 0fh 9ah 11-xxx-xxx vector setp/setpe mem8 0fh 9ah mm-xxx-xxx vector setnp/setpo mreg8 0fh 9bh 11-xxx-xxx vector setnp/setpo mem8 0fh 9bh mm-xxx-xxx vector setl/setnge mreg8 0fh 9ch 11-xxx-xxx vector setl/setnge mem8 0fh 9ch mm-xxx-xxx vector setnl/setge mreg8 0fh 9dh 11-xxx-xxx vector setnl/setge mem8 0fh 9dh mm-xxx-xxx vector setle/setng mreg8 0fh 9eh 11-xxx-xxx vector setle/setng mem8 0fh 9eh mm-xxx-xxx vector setnle/setg mreg8 0fh 9fh 11-xxx-xxx vector setnle/setg mem8 0fh 9fh mm-xxx-xxx vector sgdt mem48 0fh 01h mm-000-xxx vector sidt mem48 0fh 01h mm-001-xxx vector shl/sal mreg8, imm8 c0h 11-100-xxx short alux shl/sal mem8, imm8 c0h mm-100-xxx vector shl/sal mreg16/32, imm8 c1h 11-100-xxx short alu shl/sal mem16/32, imm8 c1h mm-100-xxx vector shl/sal mreg8, 1 d0h 11-100-xxx short alux shl/sal mem8, 1 d0h mm-100-xxx vector shl/sal mreg16/32, 1 d1h 11-100-xxx short alu table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
chapter 3 software environment 65 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information shl/sal mem16/32, 1 d1h mm-100-xxx vector shl/sal mreg8, cl d2h 11-100-xxx short alux shl/sal mem8, cl d2h mm-100-xxx vector shl/sal mreg16/32, cl d3h 11-100-xxx short alu shl/sal mem16/32, cl d3h mm-100-xxx vector shr mreg8, imm8 c0h 11-101-xxx short alux shr mem8, imm8 c0h mm-101-xxx vector shr mreg16/32, imm8 c1h 11-101-xxx short alu shr mem16/32, imm8 c1h mm-101-xxx vector shr mreg8, 1 d0h 11-101-xxx short alux shr mem8, 1 d0h mm-101-xxx vector shr mreg16/32, 1 d1h 11-101-xxx short alu shr mem16/32, 1 d1h mm-101-xxx vector shr mreg8, cl d2h 11-101-xxx short alux shr mem8, cl d2h mm-101-xxx vector shr mreg16/32, cl d3h 11-101-xxx short alu shr mem16/32, cl d3h mm-101-xxx vector shld mreg16/32, reg16/32, imm8 0fh a4h 11-xxx-xxx vector shld mem16/32, reg16/32, imm8 0fh a4h mm-xxx-xxx vector shld mreg16/32, reg16/32, cl 0fh a5h 11-xxx-xxx vector shld mem16/32, reg16/32, cl 0fh a5h mm-xxx-xxx vector shrd mreg16/32, reg16/32, imm8 0fh ach 11-xxx-xxx vector shrd mem16/32, reg16/32, imm8 0fh ach mm-xxx-xxx vector shrd mreg16/32, reg16/32, cl 0fh adh 11-xxx-xxx vector shrd mem16/32, reg16/32, cl 0fh adh mm-xxx-xxx vector sldt mreg16 0fh 00h 11-000-xxx vector sldt mem16 0fh 00h mm-000-xxx vector smsw mreg16 0fh 01h 11-100-xxx vector smsw mem16 0fh 01h mm-100-xxx vector stc f9h vector std fdh vector sti fbh vector stosb mem8, al aah long store, alux table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
66 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information stosw mem16, ax abh long store, alu stosd mem32, eax abh long store, alu str mreg16 0fh 00h 11-001-xxx vector str mem16 0fh 00h mm-001-xxx vector sub mreg8, reg8 28h 11-xxx-xxx short alux sub mem8, reg8 28h mm-xxx-xxx long load, alux, store sub mreg16/32, reg16/32 29h 11-xxx-xxx short alu sub mem16/32, reg16/32 29h mm-xxx-xxx long load, alu, store sub reg8, mreg8 2ah 11-xxx-xxx short alux sub reg8, mem8 2ah mm-xxx-xxx short load, alux sub reg16/32, mreg16/32 2bh 11-xxx-xxx short alu sub reg16/32, mem16/32 2bh mm-xxx-xxx short load, alu sub al, imm8 2ch xx-xxx-xxx short alux sub eax, imm16/32 2dh xx-xxx-xxx short alu sub mreg8, imm8 80h 11-101-xxx short alux sub mem8, imm8 80h mm-101-xxx long load, alux, store sub mreg16/32, imm16/32 81h 11-101-xxx short alu sub mem16/32, imm16/32 81h mm-101-xxx long load, alu, store sub mreg16/32, imm8 (signed ext.) 83h 11-101-xxx short alux sub mem16/32, imm8 (signed ext.) 83h mm-101-xxx long load, alux, store test mreg8, reg8 84h 11-xxx-xxx short alux test mem8, reg8 84h mm-xxx-xxx vector test mreg16/32, reg16/32 85h 11-xxx-xxx short alu test mem16/32, reg16/32 85h mm-xxx-xxx vector test al, imm8 a8h long alux test eax, imm16/32 a9h long alu test mreg8, imm8 f6h 11-000-xxx long alux test mem8, imm8 f6h mm-000-xxx long load, alux test mreg8, imm16/32 f7h 11-000-xxx long alu test mem8, imm16/32 f7h mm-000-xxx long load, alu verr mreg16 0fh 00h 11-100-xxx vector verr mem16 0fh 00h mm-100-xxx vector verw mreg16 0fh 00h 11-101-xxx vector table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
chapter 3 software environment 67 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information verw mem16 0fh 00h mm-101-xxx vector wait 9bh vector wbinvd 0fh 09h vector xadd mreg8, reg8 0fh c0h 11-100-xxx vector xadd mem8, reg8 0fh c0h mm-100-xxx vector xadd mreg16/32, reg16/32 0fh c1h 11-101-xxx vector xadd mem16/32, reg16/32 0fh c1h mm-101-xxx vector xchg reg8, mreg8 86h 11-xxx-xxx vector xchg reg8, mem8 86h mm-xxx-xxx vector xchg reg16/32, mreg16/32 87h 11-xxx-xxx vector xchg reg16/32, mem16/32 87h mm-xxx-xxx vector xchg eax, eax 90h short limm xchg eax, ecx 91h long alu, alu, alu xchg eax, edx 92h long alu, alu, alu xchg eax, ebx 93h long alu, alu, alu xchg eax, esp 94h long alu, alu, alu xchg eax, ebp 95h long alu, alu, alu xchg eax, esi 96h long alu, alu, alu xchg eax, edi 97h long alu, alu, alu xlat d7h vector xor mreg8, reg8 30h 11-xxx-xxx short alux xor mem8, reg8 30h mm-xxx-xxx long load, alux, store xor mreg16/32, reg16/32 31h 11-xxx-xxx short alu xor mem16/32, reg16/32 31h mm-xxx-xxx long load, alu, store xor reg8, mreg8 32h 11-xxx-xxx short alux xor reg8, mem8 32h mm-xxx-xxx short load, alux xor reg16/32, mreg16/32 33h 11-xxx-xxx short alu xor reg16/32, mem16/32 33h mm-xxx-xxx short load, alu xor al, imm8 34h xx-xxx-xxx short alux xor eax, imm16/32 35h xx-xxx-xxx short alu xor mreg8, imm8 80h 11-110-xxx short alux xor mem8, imm8 80h mm-110-xxx long load, alux, store xor mreg16/32, imm16/32 81h 11-110-xxx short alu table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
68 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information xor mem16/32, imm16/32 81h mm-110-xxx long load, alu, store xor mreg16/32, imm8 (signed ext.) 83h 11-110-xxx short alux xor mem16/32, imm8 (signed ext.) 83h mm-110-xxx long load, alux, store table 11. floating-point instructions instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes note f2xm1 d9h f0h short float fabs d9h f1h short float fadd st(0), st(i) d8h 11-000-xxx short float * fadd st(0), mem32real d8h mm-000-xxx short fload, float fadd st(i), st(0) dch 11-000-xxx short float * fadd st(0), mem64real dch mm-000-xxx short fload, float faddp st(i), st(0) deh 11-000-xxx short float * fbld dfh mm-100-xxx vector * fbstp dfh mm-110-xxx vector * fchs d9h e0h short float fclex dbh e2h vector fcom st(0), st(i) d8h 11-010-xxx short float * fcom st(0), mem32real d8h mm-010-xxx short fload, float fcom st(0), mem64real dch mm-010-xxx short fload, float fcomp st(0), st(i) d8h 11-011-xxx short float * fcomp st(0), mem32real d8h mm-011-xxx short fload, float fcomp st(0), mem64real dch mm-011-xxx short fload, float fcompp deh 11-011-001 short float fcos st(0) d9h ffh short float fdecstp d9h f6h short float fdiv st(0), st(i) (single precision) d8h 11-110-xxx short float * fdiv st(0), st(i) (double precision) d8h 11-110-xxx short float * fdiv st(0), st(i) (extended precision) d8h 11-110-xxx short float * note: * the last three bits of the modr/m byte select the stack entry st(i). table 10. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes
chapter 3 software environment 69 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information fdiv st(i), st(0) (single precision) dch 11-111-xxx short float * fdiv st(i), st(0) (double precision) dch 11-111-xxx short float * fdiv st(i), st(0) (extended precision) dch 11-111-xxx short float * fdiv st(0), mem32real d8h mm-110-xxx short fload, float fdiv st(0), mem64real dch mm-110-xxx short fload, float fdivp st(0), st(i) deh 11-111-xxx short float * fdivr st(0), st(i) d8h 11-110-xxx short float * fdivr st(i), st(0) dch 11-111-xxx short float * fdivr st(0), mem32real d8h mm-111-xxx short fload, float fdivr st(0), mem64real dch mm-111-xxx short fload, float fdivrp st(i), st(0) deh 11-110-xxx short float * ffree st(i) ddh 11-000-xxx short float * fiadd st(0), mem32int dah mm-000-xxx short fload, float fiadd st(0), mem16int deh mm-000-xxx short fload, float ficom st(0), mem32int dah mm-010-xxx short fload, float ficom st(0), mem16int deh mm-010-xxx short fload, float ficomp st(0), mem32int dah mm-011-xxx short fload, float ficomp st(0), mem16int deh mm-011-xxx short fload, float fidiv st(0), mem32int dah mm-110-xxx short fload, float fidiv st(0), mem16int deh mm-110-xxx short fload, float fidivr st(0), mem32int dah mm-111-xxx short fload, float fidivr st(0), mem16int deh mm-111-xxx short fload, float fild mem16int dfh mm-000-xxx short fload, float fild mem32int dbh mm-000-xxx short fload, float fild mem64int dfh mm-101-xxx short fload, float fimul st(0), mem32int dah mm-001-xxx short fload, float fimul st(0), mem16int deh mm-001-xxx short fload, float fincstp d9h f7h short float finit dbh e3h vector fist mem16int dfh mm-010-xxx short fload, float fist mem32int dbh mm-010-xxx short fload, float table 11. floating-point instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes note note: * the last three bits of the modr/m byte select the stack entry st(i).
70 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information fistp mem16int dfh mm-011-xxx short fload, float fistp mem32int dbh mm-011-xxx short fload, float fistp mem64int dfh mm-111-xxx short fload, float fisub st(0), mem32int dah mm-100-xxx short fload, float fisub st(0), mem16int deh mm-100-xxx short fload, float fisubr st(0), mem32int dah mm-101-xxx short fload, float fisubr st(0), mem16int deh mm-101-xxx short fload, float fld st(i) d9h 11-000-xxx short fload, float * fld mem32real d9h mm-000-xxx short fload, float fld mem64real ddh mm-000-xxx short fload, float fld mem80real dbh mm-101-xxx vector fld1 d9h e8h short fload, float fldcw d9h mm-101-xxx vector fldenv d9h mm-100-xxx short fload, float fldl2e d9h eah short float fldl2t d9h e9h short float fldlg2 d9h ech short float fldln2 d9h edh short float fldpi d9h ebh short float fldz d9h eeh short float fmul st(0), st(i) d8h 11-001-xxx short float * fmul st(i), st(0) dch 11-001-xxx short float * fmul st(0), mem32real d8h mm-001-xxx short fload, float fmul st(0), mem64real dch mm-001-xxx short fload, float fmulp st(0), st(i) deh 11-001-xxx short float fnop d9h d0h short float fpatan d9h f3h short float fprem d9h f8h short float fprem1 d9h f5h short float fptan d9h f2h vector frndint d9h fch short float table 11. floating-point instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes note note: * the last three bits of the modr/m byte select the stack entry st(i).
chapter 3 software environment 71 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information frstor ddh mm-100-xxx vector fsave ddh mm-110-xxx vector fscale d9h fdh short float fsin d9h feh short float fsincos d9h fbh vector fsqrt (single precision) d9h fah short float fsqrt (double precision) d9h fah short float fsqrt (extended precision) d9h fah short float fst mem32real d9h mm-010-xxx short fstore fst mem64real ddh mm-010-xxx short fstore fst st(i) ddh 11-010xxx short fstore fstcw d9h mm-111-xxx vector fstenv d9h mm-110-xxx vector fstp mem32real d9h mm-011-xxx short fstore fstp mem64real ddh mm-011-xxx short fstore fstp mem80real d9h mm-111-xxx vector fstp st(i) ddh 11-011-xxx short float fstsw ax dfh e0h vector fstsw mem16 ddh mm-111-xxx vector fsub st(0), mem32real d8h mm-100-xxx short fload, float fsub st(0), mem64real dch mm-100-xxx short fload, float fsub st(0), st(i) d8h 11-100-xxx short float fsub st(i), st(0) dch 11-101-xxx short float fsubp st(0), st(i) deh 11-101-xxx short float fsubr st(0), mem32real d8h mm-101-xxx short fload, float fsubr st(0), mem64real dch mm-101-xxx short fload, float fsubr st(0), st(i) d8h 11-100-xxx short float fsubr st(i), st(0) dch 11-101-xxx short float fsubrp st(i), st(0) deh 11-100-xxx short float ftst d9h e4h short float fucom ddh 11-100-xxx short float table 11. floating-point instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes note note: * the last three bits of the modr/m byte select the stack entry st(i).
72 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information fucomp ddh 11-101-xxx short float fucompp dah e9h short float fxam d9h e5h short float fxch d9h 11-001-xxx short float fxtract d9h f4h vector fyl2x d9h f1h short float fyl2xp1 d9h f9h short float fwait 9bh vector table 12. mmx? instructions instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 ? opcodes note emms 0fh 77h vector movd mmreg, mreg32 0fh 6eh 11-xxx-xxx short store, mload * movd mmreg, mem32 0fh 6eh mm-xxx-xxx short mload movd mreg32, mmreg 0fh 7eh 11-xxx-xxx short mstore, load * movd mem32, mmreg 0fh 7eh mm-xxx-xxx short mstore movq mmreg1, mmreg2 0fh 6fh 11-xxx-xxx short meu movq mmreg, mem64 0fh 6fh mm-xxx-xxx short mload movq mmreg1, mmreg2 0fh 7fh 11-xxx-xxx short meu movq mem64, mmreg 0fh 7fh mm-xxx-xxx short mstore packssdw mmreg1, mmreg2 0fh 6bh 11-xxx-xxx short meu packssdw mmreg, mem64 0fh 6bh mm-xxx-xxx short mload, meu packsswb mmreg1, mmreg2 0fh 63h 11-xxx-xxx short meu packsswb mmreg, mem64 0fh 64h mm-xxx-xxx short mload, meu packuswb mmreg1, mmreg2 0fh 67h 11-xxx-xxx short meu packuswb mmreg, mem64 0fh 67h mm-xxx-xxx short mload, meu paddb mmreg1, mmreg2 0fh fch 11-xxx-xxx short meu paddb mmreg, mem64 0fh fch mm-xxx-xxx short mload, meu note: * bits 2, 1, and 0 of the modr/m byte select the integer register. table 11. floating-point instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes note note: * the last three bits of the modr/m byte select the stack entry st(i).
chapter 3 software environment 73 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information paddd mmreg1, mmreg2 0fh feh 11-xxx-xxx short meu paddd mmreg, mem64 0fh feh mm-xxx-xxx short mload, meu paddsb mmreg1, mmreg2 0fh ech 11-xxx-xxx short meu paddsb mmreg, mem64 0fh ech mm-xxx-xxx short mload, meu paddsw mmreg1, mmreg2 0fh edh 11-xxx-xxx short meu paddsw mmreg, mem64 0fh edh mm-xxx-xxx short mload, meu paddusb mmreg1, mmreg2 0fh dch 11-xxx-xxx short meu paddusb mmreg, mem64 0fh dch mm-xxx-xxx short mload, meu paddusw mmreg1, mmreg2 0fh ddh 11-xxx-xxx short meu paddusw mmreg, mem64 0fh ddh mm-xxx-xxx short mload, meu paddw mmreg1, mmreg2 0fh fdh 11-xxx-xxx short meu paddw mmreg, mem64 0fh fdh mm-xxx-xxx short mload, meu pand mmreg1, mmreg2 0fh dbh 11-xxx-xxx short meu pand mmreg, mem64 0fh dbh mm-xxx-xxx short mload, meu pandn mmreg1, mmreg2 0fh dfh 11-xxx-xxx short meu pandn mmreg, mem64 0fh dfh mm-xxx-xxx short mload, meu pcmpeqb mmreg1, mmreg2 0fh 74h 11-xxx-xxx short meu pcmpeqb mmreg, mem64 0fh 74h mm-xxx-xxx short mload, meu pcmpeqd mmreg1, mmreg2 0fh 76h 11-xxx-xxx short meu pcmpeqd mmreg, mem64 0fh 76h mm-xxx-xxx short mload, meu pcmpeqw mmreg1, mmreg2 0fh 75h 11-xxx-xxx short meu pcmpeqw mmreg, mem64 0fh 75h mm-xxx-xxx short mload, meu pcmpgtb mmreg1, mmreg2 0fh 64h 11-xxx-xxx short meu pcmpgtb mmreg, mem64 0fh 64h mm-xxx-xxx short mload, meu pcmpgtd mmreg1, mmreg2 0fh 66h 11-xxx-xxx short meu pcmpgtd mmreg, mem64 0fh 66h mm-xxx-xxx short mload, meu pcmpgtw mmreg1, mmreg2 0fh 65h 11-xxx-xxx short meu pcmpgtw mmreg, mem64 0fh 65h mm-xxx-xxx short mload, meu pmaddwd mmreg1, mmreg2 0fh f5h 11-xxx-xxx short meu pmaddwd mmreg, mem64 0fh f5h mm-xxx-xxx short mload, meu pmulhw mmreg1, mmreg2 0fh e5h 11-xxx-xxx short meu table 12. mmx? instructions (continued) instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 ? opcodes note note: * bits 2, 1, and 0 of the modr/m byte select the integer register.
74 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information pmulhw mmreg, mem64 0fh e5h mm-xxx-xxx short mload, meu pmullw mmreg1, mmreg2 0fh d5h 11-xxx-xxx short meu pmullw mmreg, mem64 0fh d5h mm-xxx-xxx short mload, meu por mmreg1, mmreg2 0fh ebh 11-xxx-xxx short meu por mmreg, mem64 0fh ebh mm-xxx-xxx short mload, meu psllw mmreg1, mmreg2 0fh f1h 11-xxx-xxx short meu psllw mmreg, mem64 0fh f1h 11-xxx-xxx short mload, meu psllw mmreg, imm8 0fh 71h 11-110-xxx short meu pslld mmreg1, mmreg2 0fh f2h 11-xxx-xxx short meu pslld mmreg, mem64 0fh f2h 11-xxx-xxx short meu pslld mmreg, imm8 0fh 72h 11-110-xxx short meu psllq mmreg1, mmreg2 0fh f3h 11-xxx-xxx short meu psllq mmreg, mem64 0fh f3h 11-xxx-xxx short meu psllq mmreg, imm8 0fh 73h 11-110-xxx short meu psraw mmreg1, mmreg2 0fh e1h 11-xxx-xxx short meu psraw mmreg, mem64 0fh e1h 11-xxx-xxx short meu psraw mmreg, imm8 0fh 71h 11-100-xxx short meu psrad mmreg1, mmreg2 0fh e2h 11-xxx-xxx short meu psrad mmreg, mem64 0fh e2h 11-xxx-xxx short meu psrad mmreg, imm8 0fh 72h 11-100-xxx short meu psraq mmreg1, mmreg2 0fh e3h 11-xxx-xxx short meu psraq mmreg, mem64 0fh e3h 11-xxx-xxx short meu psraq mmreg, imm8 0fh 73h 11-100-xxx short meu psrlw mmreg1, mmreg2 0fh d1h 11-xxx-xxx short meu psrlw mmreg, mem64 0fh d1h 11-xxx-xxx short meu psrlw mmreg, imm8 0fh 71h 11-010-xxx short meu psrld mmreg1, mmreg2 0fh d2h 11-xxx-xxx short meu psrld mmreg, mem64 0fh d2h 11-xxx-xxx short meu psrld mmreg, imm8 0fh 72h 11-010-xxx short meu psrlq mmreg1, mmreg2 0fh d3h 11-xxx-xxx short meu psrlq mmreg, mem64 0fh d3h 11-xxx-xxx short meu table 12. mmx? instructions (continued) instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 ? opcodes note note: * bits 2, 1, and 0 of the modr/m byte select the integer register.
chapter 3 software environment 75 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information psrlq mmreg, imm8 0fh 73h 11-010-xxx short meu psubb mmreg1, mmreg2 0fh f8h 11-xxx-xxx short meu psubb mmreg, mem64 0fh f8h mm-xxx-xxx short mload, meu psubd mmreg1, mmreg2 0fh fah 11-xxx-xxx short meu psubd mmreg, mem64 0fh fah mm-xxx-xxx short mload, meu psubsb mmreg1, mmreg2 0fh e8h 11-xxx-xxx short meu psubsb mmreg, mem64 0fh e8h mm-xxx-xxx short mload, meu psubsw mmreg1, mmreg2 0fh e9h 11-xxx-xxx short meu psubsw mmreg, mem64 0fh e9h mm-xxx-xxx short mload, meu psubusb mmreg1, mmreg2 0fh d8h 11-xxx-xxx short meu psubusb mmreg, mem64 0fh d8h mm-xxx-xxx short mload, meu psubusw mmreg1, mmreg2 0fh d9h 11-xxx-xxx short meu psubusw mmreg, mem64 0fh d9h mm-xxx-xxx short mload, meu psubw mmreg1, mmreg2 0fh f9h 11-xxx-xxx short meu psubw mmreg, mem64 0fh f9h mm-xxx-xxx short mload, meu punpckhbw mmreg1, mmreg2 0fh 68h 11-xxx-xxx short meu punpckhbw mmreg, mem64 0fh 68h mm-xxx-xxx short mload, meu punpckhwd mmreg1, mmreg2 0fh 69h 11-xxx-xxx short meu punpckhwd mmreg, mem64 0fh 69h mm-xxx-xxx short mload, meu punpckhdq mmreg1, mmreg2 0fh 6ah 11-xxx-xxx short meu punpckhdq mmreg, mem64 0fh 6ah mm-xxx-xxx short mload, meu punpcklbw mmreg1, mmreg2 0fh 60h 11-xxx-xxx short meu punpcklbw mmreg, mem64 0fh 60h mm-xxx-xxx short mload, meu punpcklwd mmreg1, mmreg2 0fh 61h 11-xxx-xxx short meu punpcklwd mmreg, mem64 0fh 61h mm-xxx-xxx short mload, meu punpckldq mmreg1, mmreg2 0fh 62h 11-xxx-xxx short meu punpckldq mmreg, mem64 0fh 62h mm-xxx-xxx short mload, meu pxor mmreg1, mmreg2 0fh efh 11-xxx-xxx short meu pxor mmreg, mem64 0fh efh mm-xxx-xxx short mload, meu table 12. mmx? instructions (continued) instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 ? opcodes note note: * bits 2, 1, and 0 of the modr/m byte select the integer register.
76 software environment chapter 3 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 4 logic symbol diagram 77 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 4 logic symbol diagram a20m# a[31:3] ap ads# adsc# apchk# be[7:0]# ahold boff# breq hlda hold d/c# ewbe# lock# m/io# na# scyc w/r# cache# ken# pcd pwt wb/wt# clock bus arbitration clk bf[2:0] tck tdi tdo tms trst# brdy# brdyc# d[63:0] dp[7:0] pchk# eads# hit# hitm# inv ferr# ignne# flush# init intr nmi reset smi# smiact# stpclk# jtag test data and data parity inquire cycles floating-point error handling external interrupts, smm, reset and initialization address and address parity cycle definition and control cache control amd-k6 ? processor voltage detection vcc2det
78 logic symbol diagram chapter 4 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 5 signal descriptions 79 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5 signal descriptions 5.1 a20m# (address bit 20 mask) input summary a20m# is used to simulate the behavior of the 8086 when running in real mode. the assertion of a20m# causes the processor to force bit 20 of the physical address to 0 prior to accessing the cache or driving out a memory bus cycle. the clearing of address bit 20 maps addresses that wrap above 1 mbyte to addresses below 1 mbyte. sampled the processor samples a20m# as a level-sensitive input on every clock edge. the system logic can drive the signal either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. the following list explains the effects of the processor sampling a20m# asserted under various conditions: n inquire cycles and writeback cycles are not affected by the state of a20m#. n the assertion of a20m# in system management mode (smm) is ignored. n when a20m# is sampled asserted in protected mode, it causes unpredictable processor operation. a20m# is only defined in real mode. n to ensure that a20m# is recognized before the first ads# occurs following the negation of reset, a20m# must be sampled asserted on the same clock edge that reset is sampled negated or on one of the two subsequent clock edges. n to ensure a20m# is recognized before the execution of an instruction, a serializing instruction must be executed between the instruction that asserts a20m# and the targeted instruction.
80 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.2 a[31:3] (address bus) a[31:5] bidirectional, a[4:3] output summary a[31:3] contain the physical address for the current bus cycle. the processor drives addresses on a[31:3] during memory and i/o cycles, and cycle definition information during special bus cycles. the processor samples addresses on a[31:5] during inquire cycles. driven, sampled, and floated as outputs: a[31:3] are driven valid off the same clock edge as ads# and remain in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. a[31:3] are driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. the processor continues to drive the address bus while the bus is idle. as inputs: the processor samples a[31:5] during inquire cycles on the clock edge on which eads# is sampled asserted. even though a4 and a3 are not used during the inquire cycle, they must be driven to a valid state and must meet the same timings as a[31:5]. a[31:3] are floated off the clock edge that ahold or boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. the processor resumes driving a[31:3] off the clock edge on which the processor samples ahold or boff# negated and off the clock edge on which the processor negates hlda.
chapter 5 signal descriptions 81 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.3 ads# (address strobe) output summary the assertion of ads# indicates the beginning of a new bus cycle. the address bus and all cycle definition signals corresponding to this bus cycle are driven valid off the same clock edge as ads#. driven and floated ads# is asserted for one clock at the beginning of each bus cycle. for non-pipelined cycles, ads# can be asserted as early as the clock edge after the clock edge on which the last expected brdy# of the cycle is sampled asserted, resulting in a single idle state between cycles. for pipelined cycles if the processor is prepared to start a new cycle, ads# can be asserted as early as one clock edge after na# is sampled asserted. if ahold is sampled asserted, ads# is only driven in order to perform a writeback cycle due to an inquire cycle that hits a modified cache line. the processor floats ads# off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. 5.4 adsc# (address strobe copy) output summary adsc# has the identical function and timing as ads#. in the event ads# becomes too heavily loaded due to a large fanout in a system, adsc# can be used to split the load across two outputs, which improves timing.
82 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.5 ahold (address hold) input summary ahold can be asserted by the system to initiate one or more inquire cycles. to allow the system to drive the address bus during an inquire cycle, the processor floats a[31:3] and ap off the clock edge on which ahold is sampled asserted. the data bus and all other control and status signals remain under the control of the processor and are not floated. this allows a bus cycle that is in progress when ahold is sampled asserted to continue to completion. the processor resumes driving the address bus off the clock edge on which ahold is sampled negated. if ahold is sampled asserted, ads# is only asserted in order to perform a writeback cycle due to an inquire cycle that hits a modified cache line. sampled the processor samples ahold on every clock edge. ahold is recognized while init and reset are sampled asserted.
chapter 5 signal descriptions 83 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.6 ap (address parity) bidirectional summary ap contains the even parity bit for cache line addresses driven and sampled on a[31:5]. even parity means that the total number of 1 bits on ap and a[31:5] is even. (a4 and a3 are not used for the generation or checking of address parity because these bits are not required to address a cache line.) ap is driven by the processor during processor-initiated cycles and is sampled by the processor during inquire cycles. if ap does not reflect even parity during an inquire cycle, the processor asserts apchk# to indicate an address bus parity check. the processor does not take an internal exception as the result of detecting an address bus parity check, and system logic must respond appropriately to the assertion of this signal. driven, sampled, and floated as an output: the processor drives ap valid off the clock edge on which ads# is asserted until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. ap is driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. the processor continues to drive ap while the bus is idle. as an input: the processor samples ap during inquire cycles on the clock edge on which eads# is sampled asserted. the processor floats ap off the clock edge that ahold or boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. the processor resumes driving ap off the clock edge on which the processor samples ahold or boff# negated and off the clock edge on which the processor negates hlda.
84 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.7 apchk# (address parity check) output summary if the processor detects an address parity error during an inquire cycle, apchk# is asserted for one clock. the processor does not take an internal exception as the result of detecting an address bus parity check, and system logic must respond appropriately to the assertion of this signal. the processor ensures that apchk# does not glitch, enabling the signal to be used as a clocking source for system logic. driven apchk# is driven valid the clock edge after the clock edge on which the processor samples eads# asserted. it is negated off the next clock edge. apchk # is always driven except in tri-state test mode.
chapter 5 signal descriptions 85 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.8 be[7:0]# (byte enables) output summary be[7:0]# are used by the processor to indicate the valid data bytes during a write cycle and the requested data bytes during a read cycle. the byte enables can be used to derive address bits a[2:0] , which are not physically part of the processors address bus. the processor checks and generates valid data parity for the data bytes that are valid as defined by the byte enables. the eight byte enables correspond to the eight bytes of the data bus as follows: the processor expects data to be driven by the system logic on all eight bytes of the data bus during a burst cache-line read cycle, independent of the byte enables that are asserted. the byte enables are also used to distinguish between special bus cycles as defined in table 19 on page 119. driven and floated be[7:0]# are driven off the same clock edge as ads# and remain in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. be[7:0]# are driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. the processor floats be[7:0]# off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. unlike the address bus, be[7:0]# are not floated in response to ahold. n be7#: d[63:56] n be3#: d[31:24] n be6#: d[55:48] n be2#: d[23:16] n be5#: d[47:40] n be1#: d[15:8] n be4#: d[39:32] n be0#: d[7:0]
86 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.9 bf[2:0] (bus frequency) inputs, internal pullups summary bf[2:0] determine the internal operating frequency of the processor. the frequency of the clk input signal is multiplied internally by a ratio determined by the state of these signals as defined in table 13. bf[2:0] have weak internal pullups and default to the 3.5 multiplier if left unconnected. sampled bf[2:0] are sampled during the falling transition of reset. they must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of reset. table 13. processor-to-bus clock ratios state of bf[2:0] inputs processor-clock to bus-clock ratio 100b 2.5x 101b 3.0x 110b 2.0x 111b 3.5x 000b 4.5x 001b 5.0x 010b 4.0x 011b 5.5x
chapter 5 signal descriptions 87 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.10 boff# (backoff) input summary if boff# is sampled asserted, the processor unconditionally aborts any cycles in progress and transitions to a bus hold state by floating the following signals: a[31:3], ads#, adsc#, ap, be[7:0]#, cache#, d[63:0], d/c#, dp[7:0], lock#, m/io#, pcd, pwt, scyc, and w/r#. these signals remain floated until boff# is sampled negated. this allows an alternate bus master or the system to control the bus. when boff# is sampled negated, any processor cycle that was aborted due to the assertion of boff# is restarted from the beginning of the cycle, regardless of the number of transfers that were completed. if boff# is sampled asserted on the same clock edge as brdy# of a bus cycle of any length, then boff# takes precedence over the brdy#. in this case, the cycle is aborted and restarted after boff# is sampled negated. sampled boff# is sampled on every clock edge. the processor floats its bus signals off the clock edge on which boff# is sampled asserted. these signals remain floated until the clock edge on which boff# is sampled negated. boff# is recognized while init and reset are sampled asserted.
88 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.11 brdy# (burst ready) input, internal pullup summary brdy# is asserted to the processor by system logic to indicate either that the data bus is being driven with valid data during a read cycle or that the data bus has been latched during a write cycle. if necessary, the system logic can insert bus cycle wait states by negating brdy# until it is ready to continue the data transfer. brdy# is also used to indicate the completion of special bus cycles. sampled brdy# is sampled every clock edge within a bus cycle starting with the clock edge after the clock edge that negates ads#. brdy# is ignored while the bus is idle. the processor samples the following inputs on the clock edge on which brdy# is sampled asserted: d[63:0], dp[7:0], and ken# during read cycles, ewbe# during write cycles, and wb/wt# during read and write cycles. if na# is sampled asserted prior to brdy#, then ken# and wb/wt# are sampled on the clock edge on which na# is sampled asserted. the number of times the processor expects to sample brdy# asserted depends on the type of bus cycle, as follows: n one time for a single-transfer cycle, a special bus cycle, or each of two cycles in an interrupt acknowledge sequence n four times for a burst cycle (once for each data transfer) brdy# can be held asserted for four consecutive clocks throughout the four transfers of the burst, or it can be negated to insert wait states.
chapter 5 signal descriptions 89 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.12 brdyc# (burst ready copy) input, internal pullup summary brdyc# has the identical function as brdy#. in the event brdy# becomes too heavily loaded due to a large fanout or loading in a system, brdyc# can be used to reduce this loading, which improves timing. in addition, brdyc# is sampled when reset is negated to configure the drive strength of a[20:3], ads#, hitm#, and w/r#. if brdyc# is 0 during the falling transition of reset, these particular outputs are configured using higher drive strengths than the standard strength. if brdyc# is 1 during the falling transition of reset, the standard strength is selected. sampled brdyc# is sampled every clock edge within a bus cycle starting with the clock edge after the clock edge that negates ads#. brdyc# is also sampled during the falling transition of reset. if reset is driven synchronously, brdyc# must meet the specified hold time relative to the negation of reset. if reset is driven asynchronously, the minimum setup and hold time for brdyc# relative to the negation of reset is two clocks.
90 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.13 breq (bus request) output summary breq is asserted by the processor to request the bus in order to complete an internally pending bus cycle. the system logic can use breq to arbitrate among the bus participants. if the processor does not own the bus, breq is asserted until the processor gains access to the bus in order to begin the pending cycle or until the processor no longer needs to run the pending cycle. if the processor currently owns the bus, breq is asserted with ads#. the processor asserts breq for each assertion of ads# but does not necessarily assert ads# for each assertion of breq. driven breq is asserted off the same clock edge on which ads# is asserted. breq can also be asserted off any clock edge, independent of the assertion of ads#. breq can be negated one clock edge after it is asserted. the processor always drives breq except in tri-state test mode. 5.14 cache# (cacheable access) output summary for reads, cache# is asserted to indicate the cacheability of the current bus cycle. in addition, if the processor samples ken# asserted, which indicates the driven address is cacheable, the cycle is a 32-byte burst read cycle. for write cycles, cache# is asserted to indicate the current bus cycle is a modified cache-line writeback. ken# is ignored during writebacks. if cache# is not asserted, or if ken# is sampled negated during a read cycle, the cycle is not cacheable and defaults to a single-transfer cycle. driven and floated cache# is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. cache# is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold.
chapter 5 signal descriptions 91 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.15 clk (clock) input summary the clk signal is the bus clock for the processor and is the reference for all signal timings under normal operation (except for tdi, tdo, tms, and trst#). bf[2:0] determine the internal frequency multiplier applied to clk to obtain the processors core operating frequency. (see bf[2:0] (bus frequency) on page 86 for a list of the processor-to-bus clock ratios.) sampled the clk signal must be stable a minimum of 1.0 ms prior to the negation of reset to ensure the proper operation of the processor. see clk switching characteristics on page 241 for details regarding the clk specifications. 5.16 d/c# (data/code) output summary the processor drives d/c# during a memory bus cycle to indicate whether it is addressing data or executable code. d/c# is also used to define other bus cycles, including interrupt acknowledge and special cycles. (see table 19 on page 119 for more details.) driven and floated d/c# is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. d/c# is driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. d/c# is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold.
92 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.17 d[63:0] (data bus) bidirectional summary d[63:0] represent the processors 64-bit data bus. each of the eight bytes of data that comprise this bus is qualified as valid by its corresponding byte enable. (see be[7:0]# (byte enables) on page 85.) driven, sampled, and floated as outputs: for single-transfer write cycles, the processor drives d[63:0] with valid data one clock edge after the clock edge on which ads# is asserted and d[63:0] remain in the same state until the clock edge on which brdy# is sampled asserted. if the cycle is a writebackin which case four, 8-byte transfers occurd[63:0] are driven one clock edge after the clock edge on which ads# is asserted and are subsequently changed off the clock edge on which each brdy# assertion of the burst cycle is sampled. if the assertion of ads# represents a pipelined write cycle that follows a read cycle, the processor does not drive d[63:0] until it is certain that contention on the data bus will not occur. in this case, d[63:0] are driven the clock edge after the last expected brdy# of the previous cycle is sampled asserted. as inputs: during read cycles, the processor samples d[63:0] on the clock edge on which brdy# is sampled asserted. the processor always floats d[63:0] except when they are being driven during a write cycle as described above. in addition, d[63:0] are floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold.
chapter 5 signal descriptions 93 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.18 dp[7:0] (data parity) bidirectional summary dp[7:0] are even parity bits for each valid byte of dataas defined by be[7:0]#driven and sampled on the d[63:0] data bus. (even parity means that the total number of 1 bits within each byte of data and its respective data parity bit is even.) dp[7:0] are driven by the processor during write cycles and sampled by the processor during read cycles. if the processor detects bad parity on any valid byte of data during a read cycle, pchk# is asserted for one clock beginning the clock edge after brdy# is sampled asserted. the processor does not take an internal exception as the result of detecting a data parity check, and system logic must respond appropriately to the assertion of this signal. the eight data parity bits correspond to the eight bytes of the data bus as follows: for systems that do not support data parity, dp[7:0] should be connected to v cc3 through pullup resistors. driven, sampled, and floated as outputs: for single-transfer write cycles, the processor drives dp[7:0] with valid parity one clock edge after the clock edge on which ads# is asserted and dp[7:0] remain in the same state until the clock edge on which brdy# is sampled asserted. if the cycle is a writeback, dp[7:0] are driven one clock edge after the clock edge on which ads# is asserted and are subsequently changed off the clock edge on which each brdy# assertion of the burst cycle is sampled. as inputs: during read cycles, the processor samples dp[7:0] on the clock edge brdy# is sampled asserted. the processor always floats dp[7:0] except when they are being driven during a write cycle as described above. in addition, dp[7:0] are floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. n dp7: d[63:56] n dp3: d[31:24] n dp6: d[55:48] n dp2: d[23:16] n dp5: d[47:40] n dp1: d[15:8] n dp4: d[39:32] n dp0: d[7:0]
94 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.19 eads# (external address strobe) input summary system logic asserts eads# during a cache inquire cycle to indicate that the address bus contains a valid address. eads# can only be driven after the system logic has taken control of the address bus by asserting ahold or boff# or by receiving hlda. the processor responds to the sampling of eads# and the address bus by driving hit#, which indicates if the inquired cache line exists in the processors cache, and hitm#, which indicates if it is in the modified state. sampled if ahold or boff# is asserted by the system logic in order to execute a cache inquire cycle, the processor begins sampling eads# two clock edges after ahold or boff# is sampled asserted. if the system logic asserts hold in order to execute a cache inquire cycle, the processor begins sampling eads# two clock edges after the clock edge hlda is asserted by the processor. eads# is ignored during the following conditions: n one clock edge after the clock edge on which eads# is sampled asserted n two clock edges after the clock edge on which ads# is asserted n when the processor is driving the address bus n when the processor asserts hitm#
chapter 5 signal descriptions 95 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.20 ewbe# (external write buffer empty) input summary the system logic can negate ewbe# to the processor to indicate that its external write buffers are full and that additional data cannot be stored at this time. this causes the processor to delay the following activities until ewbe# is sampled asserted: n the commitment of write hit cycles to cache lines in the modified state or exclusive state in the processors cache n the decode and execution of an instruction that follows a currently-executing serializing instruction n the assertion or negation of smiact# n the entering of the halt state and the stop grant state negating ewbe# does not prevent the completion of any type of cycle that is currently in progress. sampled the processor samples ewbe# on each clock edge that brdy# is sampled asserted during all memory write cycles (except writeback cycles), i/o write cycles, and special bus cycles. if ewbe# is sampled negated, it is sampled on every clock edge until it is asserted, and then it is ignored until brdy# is sampled asserted in the next write cycle or special cycle.
96 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.21 ferr# (floating-point error) output summary the assertion of ferr# indicates the occurrence of an unmasked floating-point exception resulting from the execution of a floating-point instruction. this signal is provided to allow the system logic to handle this exception in a manner consistent with ibm-compatible pc/at systems. see handling floating-point exceptions on page 189 for a system logic implementation that supports floating-point exceptions. the state of the numeric error (ne) bit in cr0 does not affect the ferr# signal. the processor ensures that ferr# does not glitch, enabling the signal to be used as a clocking source for system logic. driven the processor asserts ferr# on the instruction boundary of the next floating-point instruction, mmx instruction, or wait instruction that occurs following the floating-point instruction that caused the unmasked floating-point exceptionthat is, ferr# is not asserted at the time the exception occurs. the ignne# signal does not affect the assertion of ferr#. ferr# is negated during the following conditions: n following the successful execution of the floating-point instructions fclex, finit, fsave, and fstenv n under certain circumstances, following the successful execution of the floating-point instructions fldcw, fldenv, and frstor, which load the floating-point status word or the floating-point control word n following the falling transition of reset ferr# is always driven except in tri-state test mode. see ignne# (ignore numeric exception) on page 100 for more details on floating-point exceptions.
chapter 5 signal descriptions 97 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.22 flush# (cache flush) input summary in response to sampling flush# asserted, the processor writes back any data cache lines that are in the modified state, invalidates all lines in the instruction and data caches, and then executes a flush acknowledge special cycle. (see table 19 on page 119 for the bus definition of special cycles.) in addition, flush# is sampled when reset is negated to determine if the processor enters tri-state test mode. if flush# is 0 during the falling transition of reset, the processor enters tri-state test mode instead of performing the normal reset functions. sampled flush# is sampled and latched as a falling edge-sensitive signal. during normal operation (not reset), flush# is sampled on every clock edge but is not recognized until the next instruction boundary. if flush# is asserted synchronously, it can be asserted for a minimum of one clock. if flush# is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. flush# is also sampled during the falling transition of reset. if reset and flush# are driven synchronously, flush# is sampled on the clock edge prior to the clock edge on which reset is sampled negated. if reset is driven asynchronously, the minimum setup and hold time for flush#, relative to the negation of reset, is two clocks.
98 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.23 hit# (inquire cycle hit) output summary the processor asserts hit# during an inquire cycle to indicate that the cache line is valid within the processors instruction or data cache (also known as a cache hit). the cache line can be in the modified, exclusive, or shared state. driven hit# is always drivenexcept in tri-state test modeand only changes state the clock edge after the clock edge on which eads# is sampled asserted. it is driven in the same state until the next inquire cycle. 5.24 hitm# (inquire cycle hit to modified line) output summary the processor asserts hitm# during an inquire cycle to indicate that the cache line exists in the processors data cache in the modified state. the processor performs a writeback cycle as a result of this cache hit. if an inquire cycle hits a cache line that is currently being written back, the processor asserts hitm# but does not execute another writeback cycle. the system logic must not expect the processor to assert ads# each time hitm# is asserted. driven hitm# is always drivenexcept in tri-state test modeand, in particular, is driven to represent the result of an inquire cycle the clock edge after the clock edge on which eads# is sampled asserted. if hitm# is negated in response to the inquire address, it remains negated until the next inquire cycle. if hitm# is asserted in response to the inquire address, it remains asserted throughout the writeback cycle and is negated one clock edge after the last brdy# of the writeback is sampled asserted.
chapter 5 signal descriptions 99 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.25 hlda (hold acknowledge) output summary when hold is sampled asserted, the processor completes the current bus cycles, floats the processor bus, and asserts hlda in an acknowledgment that these events have been completed. the processor does not assert hlda until the completion of a locked sequence of cycles. while hlda is asserted, another bus master can drive cycles on the bus, including inquire cycles to the processor. the following signals are floated when hlda is asserted: a[31:3], ads#, adsc#, ap, be[7:0]#, cache#, d[63:0], d/c#, dp[7:0], lock#, m/io#, pcd, pwt, scyc, and w/r#. the processor ensures that hlda does not glitch. driven hlda is always driven except in tri-state test mode. if a processor cycle is in progress while hold is sampled asserted, hlda is asserted one clock edge after the last brdy# of the cycle is sampled asserted. if the bus is idle, hlda is asserted one clock edge after hold is sampled asserted. hlda is negated one clock edge after the clock edge on which hold is sampled negated. the assertion of hlda is independent of the sampled state of boff#. the processor floats the bus every clock in which hlda is asserted. 5.26 hold (bus hold request) input summary the system logic can assert hold to gain control of the processors bus. when hold is sampled asserted, the processor completes the current bus cycles, floats the processor bus, and asserts hlda in an acknowledgment that these events have been completed. sampled the processor samples hold on every clock edge. if a processor cycle is in progress while hold is sampled asserted, hlda is asserted one clock edge after the last brdy# of the cycle is sampled asserted. if the bus is idle, hlda is asserted one clock edge after hold is sampled asserted. hold is recognized while init and reset are sampled asserted.
100 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.27 ignne# (ignore numeric exception) input summary ignne#, in conjunction with the numeric error (ne) bit in cr0, is used by the system logic to control the effect of an unmasked floating-point exception on a previous floating-point instruction during the execution of a floating-point instruction, mmx instruction, or the wait instructionhereafter referred to as the target instruction. if an unmasked floating-point exception is pending and the target instruction is considered error-sensitive, then the relationship between ne and ignne# is as follows: n if ne = 0, then: ? if ignne# is sampled asserted, the processor ignores the floating-point exception and continues with the execution of the target instruction. ? if ignne# is sampled negated, the processor waits until it samples ignne#, intr, smi#, nmi, or init asserted. if ignne# is sampled asserted while waiting, the processor ignores the floating-point exception and continues with the execution of the target instruction. if intr, smi#, nmi, or init is sampled asserted while waiting, the processor handles its assertion appropriately. n if ne = 1, the processor invokes the int 10h exception handler. if an unmasked floating-point exception is pending and the target instruction is considered error-insensitive, then the processor ignores the floating-point exception and continues with the execution of the target instruction. ferr# is not affected by the state of the ne bit or ignne#. ferr# is always asserted at the instruction boundary of the target instruction that follows the floating-point instruction that caused the unmasked floating-point exception. this signal is provided to allow the system logic to handle exceptions in a manner consistent with ibm-compatible pc/at systems.
chapter 5 signal descriptions 101 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information sampled the processor samples ignne# as a level-sensitive input on every clock edge. the system logic can drive the signal either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. 5.28 init (initialization) input summary the assertion of init causes the processor to empty its pipelines, to initialize most of its internal state, and to branch to address ffff_fff0hthe same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the mmx state, model-specific registers, the cd and nw bits of the cr0 register, and other specific internal resources. init can be used as an accelerator for 80286 code that requires a reset to exit from protected mode back to real mode. sampled init is sampled and latched as a rising edge-sensitive signal. init is sampled on every clock edge but is not recognized until the next instruction boundary. during an i/o write cycle, it must be sampled asserted a minimum of three clock edges before brdy# is sampled asserted if it is to be recognized on the boundary between the i/o write instruction and the following instruction. if init is asserted synchronously, it can be asserted for a minimum of one clock. if it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks.
102 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.29 intr (maskable interrupt) input summary intr is the systems maskable interrupt input to the processor. when the processor samples and recognizes intr asserted, the processor executes a pair of interrupt acknowledge bus cycles and then jumps to the interrupt service routine specified by the interrupt number that was returned during the interrupt acknowledge sequence. the processor only recognizes intr if the interrupt flag (if) in the eflags register equals 1. sampled the processor samples intr as a level-sensitive input on every clock edge, but the interrupt request is not recognized until the next instruction boundary. the system logic can drive intr either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. in order to be recognized, intr must remain asserted until an interrupt acknowledge sequence is complete. 5.30 inv (invalidation request) input summary during an inquire cycle, the state of inv determines whether an addressed cache line that is found in the processors instruction or data cache transitions to the invalid state or the shared state. if inv is sampled asserted during an inquire cycle, the processor transitions the cache line (if found) to the invalid state, regardless of its previous state. if inv is sampled negated during an inquire cycle, the processor transitions the cache line (if found) to the shared state. in either case, if the cache line is found in the modified state, the processor writes it back to memory before changing its state. sampled inv is sampled on the clock edge on which eads# is sampled asserted.
chapter 5 signal descriptions 103 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.31 ken# (cache enable) input summary if ken# is sampled asserted, it indicates that the address presented by the processor is cacheable. if ken# is sampled asserted and the processor intends to perform a cache-line fill (signified by the assertion of cache#), the processor executes a 32-byte burst read cycle and expects to sample brdy# asserted a total of four times. if ken# is sampled negated during a read cycle, a single-transfer cycle is executed and the processor does not cache the data. for write cycles, cache# is asserted to indicate the current bus cycle is a modified cache-line writeback. ken# is ignored during writebacks. if pcd is asserted during a bus cycle, the processor does not cache any data read during that cycle, regardless of the state of ken#. ( see pcd (page cache disable) on page 107 for more details.) if the processor has sampled the state of ken# during a cycle, and that cycle is aborted due to the sampling of boff# asserted, the system logic must ensure that ken# is sampled in the same state when the processor restarts the aborted cycle. sampled ken# is sampled on the clock edge on which the first brdy# or na# of a read cycle is sampled asserted. if the read cycle is a burst, ken# is ignored during the last three assertions of brdy#. ken# is sampled during read cycles only when cache# is asserted.
104 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.32 lock# (bus lock) output summary the processor asserts lock# during a sequence of bus cycles to ensure that the cycles are completed without allowing other bus masters to intervene. locked operations consist of two to five bus cycles. lock# is asserted during the following operations: n an interrupt acknowledge sequence n descriptor table accesses n page directory and page table accesses n xchg instruction n an instruction with an allowable lock prefix in order to ensure that locked operations appear on the bus and are visible to the entire system, any data operands addressed during a locked cycle that reside in the processors cache are flushed and invalidated from the cache prior to the locked operation. if the cache line is in the modified state, it is written back and invalidated prior to the locked operation. likewise, any data read during a locked operation is not cached. the processor ensures that lock# does not glitch. driven and floated during a locked cycle, lock# is asserted off the same clock edge on which ads# is asserted and remains asserted until the last brdy# of the last bus cycle is sampled asserted. the processor negates lock# for at least one clock between consecutive sequences of locked operations to allow the system logic to arbitrate for the bus. lock# is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold. when lock# is floated due to boff# sampled asserted, the system logic is responsible for preserving the lock condition while lock# is in the high-impedance state.
chapter 5 signal descriptions 105 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.33 m/io# (memory or i/o) output summary the processor drives m/io# during a bus cycle to indicate whether it is addressing the memory or i/o space. if m/io# = 1, the processor is addressing memory or a memory-mapped i/o port as the result of an instruction fetch or an instruction that loads or stores data. if m/io# = 0, the processor is addressing an i/o port during the execution of an i/o instruction. in addition, m/io# is used to define other bus cycles, including interrupt acknowledge and special cycles. (see table 19 on page 119 for more details.) driven and floated m/io# is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. m/io# is driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. m/io# is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold.
10 6 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.34 na# (next address) input summary system logic asserts na# to indicate to the processor that it is ready to accept another bus cycle pipelined into the previous bus cycle. ads#, along with address and status signals, can be asserted as early as one clock edge after na# is sampled asserted if the processor is prepared to start a new cycle. because the processor allows a maximum of two cycles to be in progress at a time, the assertion of na# is sampled while two cycles are in progress but ads# is not asserted until the completion of the first cycle. sampled na# is sampled every clock edge during bus cycles, starting one clock edge after the clock edge that negates ads#, until the last expected brdy# of the last executed cycle is sampled asserted (with the exception of the clock edge after the clock edge that negates the ads# for a second pending cycle). because the processor latches na# when sampled, the system logic only needs to assert na# for one clock. 5.35 nmi (non-maskable interrupt) input summary when nmi is sampled asserted, the processor jumps to the interrupt service routine defined by interrupt number 02h. unlike the intr signal, software cannot mask the effect of nmi if it is sampled asserted by the processor. however, nmi is temporarily masked upon entering system management mode (smm). in addition, an interrupt acknowledge cycle is not executed because the interrupt number is predefined. if nmi is sampled asserted while the processor is executing the interrupt service routine for a previous nmi, the subsequent nmi remains pending until the completion of the execution of the iret instruction at the end of the interrupt service routine. sampled nmi is sampled and latched as a rising edge-sensitive signal. during normal operation, nmi is sampled on every clock edge but is not recognized until the next instruction boundary. if it is asserted synchronously, it can be asserted for a minimum of one clock. if it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks.
chapter 5 signal descriptions 107 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.36 pcd (page cache disable) output summary the processor drives pcd to indicate the operating systems specification of cacheability for the page being addressed. system logic can use pcd to control external caching. if pcd is asserted, the addressed page is not cached. if pcd is negated, the cacheability of the addressed page depends upon the state of cache# and ken#. the state of pcd depends upon the processors operating mode and the state of certain bits in its control registers and tlb as follows: n in real mode, or in protected and virtual-8086 modes while paging is disabled (pg bit in cr0 set to 0): pcd output = cd bit in cr0 n in protected and virtual-8086 modes while caching is enabled (cd bit in cr0 set to 0) and paging is enabled (pg bit in cr0 set to 1): ? for accesses to i/o space, page directory entries, and other non-paged accesses: pcd output = pcd bit in cr3 ? for accesses to 4-kbyte page table entries or 4-mbyte pages: pcd output = pcd bit in page directory entry ? for accesses to 4-kbyte pages: pcd output = pcd bit in page table entry driven and floated pcd is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. pcd is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold.
10 8 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.37 pchk# (parity check) output summary the processor asserts pchk# during read cycles if it detects an even parity error on one or more valid bytes of d[63:0] during a read cycle. (even parity means that the total number of 1 bits within each byte of data and its respective data parity bit is even.) the processor checks data parity for the data bytes that are valid, as defined by be[7:0]#, the byte enables. pchk# is always driven but is only asserted for memory and i/o read bus cycles and the second cycle of an interrupt acknowledge sequence. pchk# is not driven during any type of write cycles or special bus cycles. the processor does not take an internal exception as the result of detecting a data parity error, and system logic must respond appropriately to the assertion of this signal. the processor ensures that pchk# does not glitch, enabling the signal to be used as a clocking source for system logic. driven pchk# is always driven except in tri-state test mode. for each brdy# returned to the processor during a read cycle with a parity error detected on the data bus, pchk# is asserted for one clock, one clock edge after brdy# is sampled asserted.
chapter 5 signal descriptions 109 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.38 pwt (page writethrough) output summary the processor drives pwt to indicate the operating systems specification of the writeback state or writethrough state for the page being addressed. pwt, together with wb/wt#, specifies the data cache-line state during cacheable read misses and write hits to shared cache lines. (see wb/wt# (writeback or writethrough) on page 116 for more details.) the state of pwt depends upon the processors operating mode and the state of certain bits in its control registers and tlb as follows: n in real mode, or in protected and virtual-8086 modes while paging is disabled (pg bit in cr0 set to 0): pwt output = 0 (writeback state) n in protected and virtual-8086 modes while paging is enabled (pg bit in cr0 set to 1): ? for accesses to i/o space, page directory entries, and other non-paged accesses: pwt output = pwt bit in cr3 ? for accesses to 4-kbyte page table entries or 4-mbyte pages: pwt output = pwt bit in page directory entry ? for accesses to 4-kbyte pages: pwt output = pwt bit in page table entry driven and floated pwt is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. pwt is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold.
110 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.39 reset (reset) input summary when the processor samples reset asserted, it immediately flushes and initializes all internal resources and its internal state including its pipelines and caches, the floating-point state, the mmx state, and all registers, and then the processor jumps to address ffff_fff0h to start instruction execution. the signals brdyc# and flush# are sampled during the falling transition of reset to select the drive strength of selected output signals and to invoke the tri-state test mode, respectively. (see these signal descriptions for more details.) sampled reset is sampled as a level-sensitive input on every clock edge. system logic can drive the signal either synchronously or asynchronously. during the initial power-on reset of the processor, reset must remain asserted for a minimum of 1.0 ms after clk and v cc reach specification before it is negated. during a warm reset, while clk and v cc are within their specification, reset must remain asserted for a minimum of 15 clocks prior to its negation. 5.40 rsvd (reserved) summary reserved signals are a special class of pins that can be treated in one of the following ways: n as no-connect (nc) pins, in which case these pins are left unconnected n as pins connected to the system logic as defined by the industry-standard pentium interface (socket 7) n any combination of nc and socket 7 pins in any case, if the rsvd pins are treated accordingly, the normal operation of the amd-k6 processor is not adversely affected in any manner. see pin designations on page 269 for a list of the locations of the rsvd pins.
chapter 5 signal descriptions 111 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.41 scyc (split cycle) output summary the processor asserts scyc during misaligned, locked transfers on the d[63:0] data bus. the processor generates additional bus cycles to complete the transfer of misaligned data. for purposes of bus cycles, the term aligned means: n any 1-byte transfers n 2-byte and 4-byte transfers that lie within 4-byte address boundaries n 8-byte transfers that lie within 8-byte address boundaries driven and floated scyc is asserted off the same clock edge as ads#, and negated off the clock edge on which na# or the last expected brdy# of the entire locked sequence is sampled asserted. scyc is only valid during locked memory cycles. scyc is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold. 5.42 smi# (system management interrupt) input, internal pullup summary the assertion of smi# causes the processor to enter system management mode (smm). upon recognizing smi#, the processor performs the following actions, in the order shown: 1. flushes its instruction pipelines 2. completes all pending and in-progress bus cycles 3. acknowledges the interrupt by asserting smiact# after sampling ewbe# asserted 4. saves the internal processor state in smm memory 5. disables interrupts by clearing the interrupt flag (if) in eflags and disables nmi interrupts 6. jumps to the entry point of the smm service routine at the smm base physical address which defaults to 0003_8000h in smm memory
112 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information see system management mode (smm) on page 193 for more details regarding smm. sampled smi# is sampled and latched as a falling edge-sensitive signal. smi# is sampled on every clock edge but is not recognized until the next instruction boundary. if smi# is to be recognized on the instruction boundary associated with a brdy#, it must be sampled asserted a minimum of three clock edges before the brdy# is sampled asserted. if it is asserted synchronously, it can be asserted for a minimum of one clock. if it is asserted asynchronously, it must have been negated for a minimum of two clocks followed by an assertion of a minimum of two clocks. a second assertion of smi# while in smm is latched but is not recognized until the smm service routine is exited. 5.43 smiact# (system management interrupt active) output summary the processor acknowledges the assertion of smi# with the assertion of smiact# to indicate that the processor has entered system management mode (smm). the system logic can use smiact# to enable smm memory. see smi# (system management interrupt) on page 111 for more details. see system management mode (smm) on page 193 for more details regarding smm. driven the processor asserts smiact# after the last brdy# of the last pending bus cycle is sampled asserted (including all pending write cycles) and after ewbe# is sampled asserted. smiact# remains asserted until after the last brdy# of the last pending bus cycle associated with exiting smm is sampled asserted. smiact# remains asserted during any flush, internal snoop, or writeback cycle due to an inquire cycle.
chapter 5 signal descriptions 113 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.44 stpclk# (stop clock) input, internal pullup summary the assertion of stpclk# causes the processor to enter the stop grant state, during which the processors internal clock is stopped. from the stop grant state, the processor can subsequently transition to the stop clock state, in which the bus clock clk is stopped. upon recognizing stpclk#, the processor performs the following actions, in the order shown: 1. flushes its instruction pipelines 2. completes all pending and in-progress bus cycles 3. acknowledges the stpclk# assertion by executing a stop grant special bus cycle (see table 19 on page 119) 4. stops its internal clock after brdy# of the stop grant special bus cycle is sampled asserted and after ewbe# is sampled asserted 5. enters the stop clock state if the system logic stops the bus clock clk (optional) see clock control on page 223 for more details regarding clock control. sampled stpclk# is sampled as a level-sensitive input on every clock edge but is not recognized until the next instruction boundary. system logic can drive the signal either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. stpclk# must remain asserted until recognized, which is indicated by the completion of the stop grant special cycle. 5.45 tck (test clock) input, internal pullup summary tck is the clock for boundary-scan testing using the test access port (tap). see boundary-scan test access port (tap) on page 205 for details regarding the operation of the tap controller. sampled the processor always samples tck, except while trst# is asserted.
114 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.46 tdi (test data input) input, internal pullup summary tdi is the serial test data and instruction input for boundary-scan testing using the test access port (tap). see boundary-scan test access port (tap) on page 205 for details regarding the operation of the tap controller. sampled the processor samples tdi on every rising tck edge but only while in the shift-ir and shift-dr states. 5.47 tdo (test data output) output summary tdo is the serial test data and instruction output for boundary-scan testing using the test access port (tap). see boundary-scan test access port (tap) on page 205 for details regarding the operation of the tap controller. driven and floated the processor drives tdo on every falling tck edge but only while in the shift-ir and shift-dr states. tdo is floated at all other times. 5.48 tms (test mode select) input, internal pullup summary tms specifies the test function and sequence of state changes for boundary-scan testing using the test access port (tap). see boundary-scan test access port (tap) on page 205 for details regarding the operation of the tap controller. sampled the processor samples tms on every rising tck edge. if tms is sampled high for five or more consecutive clocks, the tap controller enters its test-logic-reset state, regardless of the controller state. this action is the same as that achieved by asserting trst#.
chapter 5 signal descriptions 115 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5.49 trst# (test reset) input, internal pullup summary the assertion of trst# initializes the test access port (tap) by resetting its state machine to the test-logic-reset state. see boundary-scan test access port (tap) on page 205 for details regarding the operation of the tap controller. sampled trst# is a completely asynchronous input that does not require a minimum setup and hold time relative to tck. see table 54 on page 253 for the minimum pulse width requirement. 5.50 vcc2det (v cc2 detect) output summary vcc2det is tied to v ss (logic level 0) to indicate to the system logic that it must supply the specified processor core voltage to the v cc2 pins. the v cc2 pins supply voltage to the processor core, independent of the voltage supplied to the i/o buffers on the v cc3 pins. driven vcc2det always equals 0 and is never floatedeven during tri-state test mode. 5.51 w/r# (write/read) output summary the processor drives w/r# to indicate whether it is performing a write or a read cycle on the bus. in addition, w/r# is used to define other bus cycles, including interrupt acknowledge and special cycles (see table 19 on page 119 for more details). driven and floated w/r# is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. w/r# is driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. w/r# is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold.
116 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 5.52 wb/wt# (writeback or writethrough) input summary wb/wt#, together with pwt, specifies the data cache-line state during cacheable read misses and write hits to shared cache lines. if wb/wt# = 0 or pwt = 1 during a cacheable read miss or write hit to a shared cache line, the accessed line is cached in the shared state. this is referred to as the writethrough state because all write cycles to this cache line are driven externally on the bus. if wb/wt# = 1 and pwt = 0 during a cacheable read miss or a write hit to a shared cache line, the accessed line is cached in the exclusive state. subsequent write hits to the same line cause its state to transition from exclusive to modified. this is referred to as the writeback state because the data cache can contain modified cache lines that are subject to be written backreferred as a writeback cycleas the result of an inquire cycle, an internal snoop, a flush operation, or the wbinvd instruction. sampled wb/wt# is sampled on the clock edge that the first brdy# or na# of a bus cycle is sampled asserted. if the cycle is a burst read, wb/wt# is ignored during the last three assertions of brdy#. wb/wt# is sampled during memory read and non-writeback write cycles and is ignored during all other types of cycles.
chapter 5 signal descriptions 117 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information table 14. input pin types name type note name type note a20m# asynchronous note 1 ignne# asynchronous note 1 ahold synchronous init asynchronous note 2 bf[2:0] synchronous note 4 intr asynchronous note 1 boff# synchronous inv synchronous brdy# synchronous ken# synchronous brdyc# synchronous note 7 na# synchronous clk clock nmi asynchronous note 2 eads# synchronous reset asynchronous note 5, 6 ewbe# synchronous smi# asynchronous note 2 flush# asynchronous note 2, 3 stpclk# asynchronous note 1 hold synchronous wb/wt# synchronous notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks. 3. flush # is also sampled during the falling transition of reset and can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which reset is sampled negated. if asserted asynchronously, flush# must meet a minimum setup and hold time of two clocks relative to the negation of reset. 4. bf[2:0] are sampled during the falling transition of reset. they must meet a minimum se tup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of r eset. 5. during the initial power-on reset of the processor, reset must remain asserted for a minimum of 1.0 ms after clk and v cc reach specification before it is negated. 6. during a warm reset, while clk and v cc are within their specification, reset must remain asserted for a minimum of 15 clocks prior to its negation. 7. brdyc# is also sampled during the falling transition of reset. if reset is driven synchronously, brdyc# must meet the specifi ed hold time relative to the negation of reset. if asserted asynchronously, brdyc# must meet a minimum setup and hold time of two clocks relative to the negation of reset.
118 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information table 15. output pin float conditions name floated at: (note 1) note name floated at: (note 1) note a[4:3] hlda, ahold, boff# note 2, 3 hitm# always driven ads# hlda, boff# note 2 hlda always driven adsc# hlda, boff# note 2 lock# hlda, boff# note 2 apchk# always driven m/io# hlda, boff# note 2 be[7:0]# hlda, boff# note 2 pcd hlda, boff# note 2 breq always driven pchk# always driven cache# hlda, boff# note 2 pwt hlda, boff# note 2 d/c# hlda, boff# note 2 scyc hlda, boff# note 2 ferr# always driven smiact# always driven hit# always driven w/r# hlda, boff# note 2 notes: 1. all outputs except vcc2det and tdo float during tri-state test mode. 2. floated off the clock edge that boff# is sampled asserted and off the clock edge that hlda is asserted. 3. floated off the clock edge that ahold is sampled asserted. table 16. input/output pin float conditions name floated at: (note 1) note a[31:5] hlda, ahold, boff# note 2,3 ap hlda, ahold, boff# note 2,3 d[63:0] hlda, boff# note 2 dp[7:0] hlda, boff# note 2 notes: 1. all outputs except vcc2det and tdo float during tri-state test mode. 2. floated off the clock edge that boff# is sampled asserted and off the clock edge that hlda is asserted. 3. floated off the clock edge that ahold is sampled asserted. table 17. test pins name type note tck clock tdi input sampled on the rising edge of tck tdo output driven on the falling edge of tck tms input sampled on the rising edge of tck trst# input asynchronous (independent of tck)
chapter 5 signal descriptions 119 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information table 18. bus cycle definition bus cycle initiated generated by processor generated by system m/io# d/c# w/r# cache# ken# code read, instruction cache line fill 1000 0 code read, noncacheable 1001 x code read, noncacheable 1 0 0 x 1 encoding for special cycle 0011 x interrupt acknowledge 0001 x i/o read 0101 x i/o write 0111 x memory read, data cache line fill 1100 0 memory read, noncacheable 1101 x memory read, noncacheable 1 1 0 x 1 memory write, data cache writeback 1110 x memory write, noncacheable 1111 x note: x means dont care table 19. special cycles special cycle a4 be7# be6# be5# be4# be3# be2# be1# be0# m/io# d/c# w/r# cache# ken# stop grant 1111110110011x flush acknowledge (flush# sampled asserted) 0111011110011x writeback (wbinvd instruction) 0111101110011x halt 0111110110011x flush (invd, wbinvd instruction) 0111111010011x shutdown 0111111100011x note: x means dont care
120 signal descriptions chapter 5 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 6 bus cycles 121 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 6 bus cycles the following sections describe and illustrate the timing and relationship of bus signals during various types of bus cycles. a representative set of bus cycles is illustrated. 6.1 timing diagrams the timing diagrams illustrate the signals on the external local bus as a function of time, as measured by the bus clock (clk). throughout this chapter, the term clock refers to a signal bus-clock cycle. a clock extends from one rising clk edge to the next rising clk edge. the processor samples and drives most signals relative to the rising edge of clk. the exceptions to this rule include the following: n bf[2:0]sampled on the falling edge of reset n flush#, brdyc#sampled on the falling edge of reset, also sampled on the rising edge of clk n all inputs and outputs are sampled relative to tck in boundary-scan test mode. inputs are sampled on the rising edge of tck, outputs are driven off of the falling edge of tck. for each signal in the timing diagrams, the high level represents 1, the low level represents 0, and the middle level represents the floating (high-impedance) state. when both the high and low levels are shown, the meaning depends on the signal. a single signal indicates dont care. in the case of bus activity, if both high and low levels are shown, it indicates the processor, alternate master, or system logic is driving a value, but this value may or may not be valid. (for example, the value on the address bus is valid only during the assertion of ads#, but addresses are also driven on the bus at other times.) figure 43 on page 122 defines the different waveform representations.
122 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 43. waveform definitions for all active-high signals, the term asserted means the signal is in the high-voltage state and the term negated means the signal is in the low-voltage state. for all active-low signals, the term asserted means the signal is in the low-voltage state and the term negated means the signal is in the high-voltage state. waveform dont care or bus is driven description signal or bus is changing from low to high signal or bus is changing from high to low bus is changing bus is changing from valid to invalid signal or bus is floating denotes multiple clock periods
chapter 6 bus cycles 123 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 6.2 bus state machine diagram figure 44. bus state machine diagram last brdy# last brdy# bus transition? no yes yes yes yes no no no no pending request? na# sampled asserted? na# sampled asserted? asserted? asserted? addr data pipe-a pipe-d idle trans bus state branch condition idle data pipeline address transition address pipeline data note: the processor transitions to the idle state on the clock edge on which boff# or reset is sampled asserted. data-na# requested data-na# last brdy# yes no asserted? pending request? no yes no yes yes na# sampled asserted? yes no
124 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information idle the processor does not drive the system bus in the idle state and remains in this state until a new bus cycle is requested. the processor enters this state off the clock edge on which the last brdy# of a cycle is sampled asserted during the following conditions: n the processor is in the data state n the processor is in the data-na# requested state and no internal pending cycle is requested in addition, the processor is forced into this state when the system logic asserts reset or boff#. the transition to this state occurs on the clock edge on which reset or boff# is sampled asserted. address in this state, the processor drives ads# to indicate the beginning of a new bus cycle by validating the address and control signals. the processor remains in this state for one clock and unconditionally enters the data state on the next clock edge. data in the data state, the processor drives the data bus during a write cycle or expects data to be returned during a read cycle. the processor remains in this state until either na# or the last brdy# is sampled asserted. if the last brdy# is sampled asserted or both the last brdy# and na# are sampled asserted on the same clock edge, the processor enters the idle state. if na# is sampled asserted first, the processor enters the data-na# requested state. data-na# requested if the processor samples na# asserted while in the data state and the current bus cycle is not completed (the last brdy# is not sampled asserted), it enters the data-na# requested state. the processor remains in this state until either the last brdy# is sampled asserted or an internal pending cycle is requested. if the last brdy# is sampled asserted before the processor drives a new bus cycle, the processor enters the idle state (no internal pending cycle is requested) or the address state (processor has a internal pending cycle). pipeline address in this state, the processor drives ads# to indicate the beginning of a new bus cycle by validating the address and control signals. in this state, the processor is still waiting for the current bus cycle to be completed (until the last brdy# is
chapter 6 bus cycles 125 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information sampled asserted). if the last brdy# is not sampled asserted, the processor enters the pipeline data state. if the processor samples the last brdy# asserted in this state, it determines if a bus transition is required between the current bus cycle and the pipelined bus cycle. a bus transition is required when the data bus direction changes between bus cycles, such as a memory write cycle followed by a memory read cycle. if a bus transition is required, the processor enters the transition state for one clock to prevent data bus contention. if a bus transition is not required, the processor enters the data state. the processor does not transition to the data-na# requested state from the pipeline address state because the processor does not begin sampling na# until it has exited the pipeline address state. pipeline data two bus cycles are concurrently executing in this state. the processor cannot issue any additional bus cycles until the current bus cycle is completed. the processor drives the data bus during write cycles or expects data to be returned during read cycles for the current bus cycle until the last brdy# of the current bus cycle is sampled asserted. if the processor samples the last brdy# asserted in this state, it determines if a bus transition is required between the current bus cycle and the pipelined bus cycle. if the bus transition is required, the processor enters the transition state for one clock to prevent data bus contention. if a bus transition is not required, the processor enters the data state (na# was not sampled asserted) or the data-na# requested state (na# was sampled asserted). transition the processor enters this state for one clock during data bus transitions and enters the data state on the next clock edge if na# is not sampled asserted. the sole purpose of this state is to avoid bus contention caused by bus transitions during pipeline operation.
126 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 6.3 memory reads and writes the amd-k6 processor performs single or burst memory bus cycles. the single-transfer memory bus cycle transfers 1, 2, 4, or 8 bytes and requires a minimum of two clocks. misaligned instructions or operands result in a split cycle, which requires multiple transactions on the bus. a burst cycle consists of four back-to-back 8-byte (64-bit) transfers on the data bus. single-transfer memory read and write figure 45 on page 127 shows a single-transfer read from memory, followed by two single-transfer writes to memory. for the memory read cycle, the processor asserts ads# for one clock to validate the bus cycle and also drives a[31:3], be[7:0]#, d/c#, w/r#, and m/io# to the bus. the processor then waits for the system logic to return the data on d[63:0] (with dp[7:0] for parity checking) and assert brdy#. the processor samples brdy# on every clock edge starting with the clock edge after the clock edge that negates ads#. see brdy# (burst ready) on page 88. during the read cycle, the processor drives pcd, pwt, and cache# to indicate its caching and cache-coherency intent for the access. the system logic returns ken# and wb/wt# to either confirm or change this intent. if the processor asserts pcd and negates cache#, the accesses are non-cacheable, even though the system logic asserts ken# during the brdy# to indicate its support for cacheability. the processor (which drives cache#) and the system logic (which drives ken#) must agree in order for an access to be cacheable. the processor can drive another cycle (in this example, a write cycle) by asserting ads# off the next clock edge after brdy# is sampled asserted. therefore, an idle clock is guaranteed between any two bus cycles. the processor drives d[63:0] with valid data one clock edge after the clock edge on which ads# is asserted. to minimize cpu idle times, the system logic stores the address and data in write buffers, returns brdy#, and performs the store to memory later. if the processor samples ewbe# negated during a write cycle, it suspends certain activities until ewbe# is sampled asserted. see ewbe# (external write buffer empty) on page 95. in figure 45, the second write cycle occurs during the execution of a serializing instruction. the processor delays the following cycle until ewbe# is sampled asserted.
chapter 6 bus cycles 127 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 45. non-pipelined single-transfer memory read/write and write delayed by ewbe# read cycle write cycle (next cycle delayed by ewbe#) write cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# breq d[63:0] dp[7:0] cache# ewbe# ken# brdy# wb/wt# addr data idle addr addr data idle data data data idle idle idle idle idle addr
128 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information misaligned single-transfer memory read and write figure 46 on page 129 shows a misaligned (split) memory read followed by a misaligned memory write. any cycle that is not aligned as defined in scyc (split cycle) on page 111 is considered misaligned. when the processor encounters a misaligned access, it determines the appropriate pair of bus cycleseach with its own ads# and brdy# required to complete the access. the amd-k6 processor performs misaligned memory reads and memory writes using least-significant bytes (lsbs) first followed by most-significant bytes (msbs). table 20 shows the order. in the first memory read cycle in figure 46, the processor reads the least-significant bytes. immediately after the processor samples brdy# asserted, it drives the second bus cycle to read the most-significant bytes to complete the misaligned transfer. similarly, the misaligned memory write cycle in figure 46 transfers the lsbs to the memory bus first. in the next cycle, after the processor samples brdy# asserted, the msbs are written to the memory bus. table 20. bus-cycle order during misaligned transfers type of access first cycle second cycle memory read lsbs msbs memory write lsbs msbs
chapter 6 bus cycles 129 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 46. misaligned single-transfer memory read and write lsb msb lsb msb memory read (misaligned) memory write (misaligned) clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] brdy# addr data data idle addr data data idle addr data data idle data addr data data idl e data
130 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information burst reads and pipelined burst reads figure 47 on page 131 shows normal burst read cycles and a pipelined burst read cycle. the amd-k6 processor drives cache# and ads# together to specify that the current bus cycle is a burst cycle. if the processor samples ken# asserted with the first brdy#, it performs burst transfers. during the burst transfers, the system logic must ignore be[7:0]# and must return all eight bytes beginning at the starting address the processor asserts on a[31:3]. depending on the starting address, the system logic must determine the successive quadword addresses (a[4:3]) for each transfer in a burst, as shown in table 21. the processor expects the second, third, and fourth quadwords to occur in the sequences shown in table 21. in figure 47, the processor drives cache# throughout all burst read cycles. in the first burst read cycle, the processor drives ads# and cache#, then samples brdy# on every clock edge starting with the clock edge after the clock edge that negates ads#. the processor samples ken# asserted on the clock edge on which the first brdy# is sampled asserted, executes a 32-byte burst read cycle, and expects to sample brdy# a total of four times. an ideal no-wait state access is shown in figure 47, whereas most system logic solutions add wait states between the transfers. the second burst read cycle illustrates a similar sequence, but the processor samples na# asserted on the same clock edge that the first brdy# is sampled asserted. na# assertion indicates the system logic is requesting the processor to output the next address early (also known as a pipeline transfer request). without waiting for the current cycle to complete, the processor drives ads# and related signals for the next burst cycle. pipelining can reduce cpu cycle-to-cycle idle times. table 21. a[4:3] address-generation sequence during bursts address driven by processor on a[4:3] a[4:3] addresses of subsequent quadwords* generated by system logic quadword 1 quadword 2 quadword 3 quadword 4 00b 01b 10b 11b 01b 00b 11b 10b 10b 11b 00b 01b 11b 10b 01b 00b note: * quadword = 8 bytes
chapter 6 bus cycles 131 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 47. burst reads and pipelined burst reads data1 data2 data3 burst read pipelined burst read addr1 addr2 addr3 burst read clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# na# d[63:0] cache# ken# brdy# addr data idle data data data addr data data data pipe-a data data data data idle -na
132 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information burst writeback figure 48 on page 133 shows a burst read followed by a writeback transaction. the amd-k6 processor initiates writebacks under the following conditions: n replacement if a cache-line fill is initiated for a cache line currently filled with valid entries, the processor uses a least-recently-allocated (lra) algorithm to select a line for replacement. before a replacement is made to a data cache line that is in the modified state, the modified line is scheduled to be written back to memory. n internal snoop the processor snoops the data cache whenever an instruction-cache line is read, and it snoops the instruction cache whenever a data cache line is written. this snooping is performed to determine whether the same address is stored in both caches, a situation that is taken to imply the occurrence of self-modifying code. if a snoop hits a data cache line in the modified state, the line is written back to memory before being invalidated. n wbinvd instruction when the processor executes a wbinvd instruction, it writes back all modified lines in the data cache and then invalidates all lines in both caches. n cache flush when the processor samples flush# asserted, it executes a flush acknowledge special cycle and writes back all modified lines in the data cache and then invalidates all lines in both caches. the processor drives writeback cycles during inquire or cache flush cycles. the writeback shown in figure 48 is caused by a cache-line replacement. the processor completes the burst read cycle that fills the cache line. immediately following the burst read cycle is the burst writeback cycle that represents the modified line to be written back to memory. d[63:0] are driven one clock edge after the clock edge on which ads# is asserted and are subsequently changed off the clock edge on which each brdy# assertion of the burst cycle is sampled.
chapter 6 bus cycles 133 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 48. burst writeback due to cache-line replacement burst read burst writeback from l1 cache clk a[31:3] be[7:0]# ads# cache# m/io# d/c# w/r# d[63:0] ken# brdy# wb/wt# addr data idle data data data addr data idle data data data
134 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 6.4 i/o read and write basic i/o read and write the processor accesses i/o when it executes an i/o instruction (for example, in or out). figure 49 shows an i/o read followed by an i/o write. the processor drives m/io# low and d/c# high during i/o cycles. in this example, the first cycle shows a single wait state i/o read cycle. it follows the same sequence as a single-transfer memory read cycle. the processor drives ads# to initiate the bus cycle, then it samples brdy# on every clock edge starting with the clock edge after the clock edge that negates ads#. the system logic must return brdy# to complete the cycle. when the processor samples brdy# asserted, it can assert ads# for the next cycle off the next clock edge. (in this example, an i/o write cycle.) the i/o write cycle is similar to a memory write cycle, but the processor drives m/io# low during an i/o write cycle. the processor asserts ads# to initiate the bus cycle. the processor drives d[63:0] with valid data one clock edge after the clock edge on which ads# is asserted. the system logic must assert brdy# when the data is properly stored to the i/o destination. the processor samples brdy# on every clock edge starting with the clock edge after the clock edge that negates ads#. in this example, two wait states are inserted while the processor waits for brdy# to be asserted. figure 49. basic i/o read and write i/o read cycle i/o write cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] brdy# addr data data idle addr data data data idle
chapter 6 bus cycles 135 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information misaligned i/o read and write table 22 shows the misaligned i/o read and write cycle order executed by the amd-k6. in figure 50, the least-significant bytes (lsbs) are transferred first. immediately after the processor samples brdy# asserted, it drives the second bus cycle to transfer the most-significant bytes (msbs) to complete the misaligned bus cycle. figure 50. misaligned i/o transfer table 22. bus-cycle order during misaligned i/o transfers type of access first cycle second cycle i/o read lsbs msbs i/o write lsbs msbs lsb msb lsb msb misaligned i/o read misaligned i/o write clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] brdy# addr data data idle addr data data idle addr data data data idle addr data data data idle lock# scyc
136 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 6.5 inquire and bus arbitration cycles the amd-k6 processor provides built-in level-one data and instruction caches. each cache is 32 kbytes and two-way set-associative. the system logic or other bus master devices can initiate an inquire cycle to maintain cache/memory coherency. in response to the inquire cycle, the processor compares the inquire address with its cache tag addresses in both caches, and, if necessary, updates the mesi state of the cache line and performs writebacks to memory. an inquire cycle can be initiated by asserting ahold, boff#, or hold. ahold is exclusively used to support inquire cycles. during ahold-initiated inquire cycles, the processor only floats the address bus. boff# provides the fastest access to the bus because it aborts any processor cycle that is in-progress, whereas ahold and hold both permit an in-progress bus cycle to complete. during hold-initiated and boff#-initiated inquire cycles, the processor floats all of its bus-driving signals. hold and hold acknowledge cycle the system logic or another bus device can assert hold to initiate an inquire cycle or to gain full control of the bus. when the amd-k6 processor samples hold asserted, it completes any in-progress bus cycle and asserts hlda to acknowledge release of the bus. the processor floats the following signals off the same clock edge that hlda is asserted: figure 51 on page 137 shows a basic hold/hlda operation. in this example, the processor samples hold asserted during the memory read cycle. it continues the current memory read cycle until brdy# is sampled asserted. the processor drives hlda and floats its outputs one clock edge after the last brdy# of the cycle is sampled asserted. the system logic can assert hold for as long as it needs to utilize the bus. the processor samples hold on every clock edge but does not assert hlda until any in-progress cycle or sequence of locked cycles is completed. n a[31:3] n dp[7:0] n ads# n lock# n ap# n m/io# n be[7:0]# n pcd n cache# n pwt n d[63:0] n scyc n d/c# n w/r#
chapter 6 bus cycles 137 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information when the processor samples hold negated during a hold acknowledge cycle, it negates hlda off the next clock edge. the processor regains control of the bus and can assert ads# off the same clock edge on which hlda is negated. figure 51. basic hold/hlda operation clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] hold hlda brdy#
138 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information hold-initiated inquire hit to shared or exclusive line figure 52 on page 139 shows a hold-initiated inquire cycle. in this example, the processor samples hold asserted during the burst memory read cycle. the processor completes the current cycle (until the last expected brdy# is sampled asserted), asserts hlda and floats its outputs as described on page 136. the system logic drives an inquire cycle within the hold acknowledge cycle. it asserts eads#, which validates the inquire address on a[31:5]. if eads# is sampled asserted before hold is sampled negated, the processor recognizes it as a valid inquire cycle. in figure 52, the processor asserts hit# and negates hitm# on the clock edge after the clock edge on which eads# is sampled asserted, indicating the current inquire cycle hit a shared or exclusive cache line. ( s hared and exclusive cache lines in the processor data or instruction cache have the same contents as the data in the external memory.) during an inquire cycle, the processor samples inv to determine whether the addressed cache line found in the processors instruction or data cache transitions to the invalid state or the shared state. in this example, the processor samples inv asserted with eads#, which invalidates the cache line. the system logic can negate hold off the same clock edge on which eads# is sampled asserted. the processor continues driving hit# in the same state until the next inquire cycle. hitm# is not asserted unless hit# is asserted.
chapter 6 bus cycles 139 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 52. hold-initiated inquire hit to shared or exclusive line burst memory read inquire clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# hit# hitm# d[63:0] ken# brdy# hold hlda eads# inv
14 0 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information hold-initiated inquire hit to modified line figure 53 on page 141 shows the same sequence as figure 52 on page 139, but in figure 53 the inquire cycle hits a modified line and the processor asserts both hit# and hitm#. in this example, the processor performs a writeback cycle immediately after the inquire cycle. it updates the modified cache line to the external memory (normally, level-two cache or dram). the processor uses the address (a[31:5]) that was latched during the inquire cycle to perform the writeback cycle. the processor asserts hitm# throughout the writeback cycle and negates hitm# one clock edge after the last expected brdy# of the writeback is sampled asserted. when the processor samples eads# during the inquire cycle, it also samples inv to determine the cache line mesi state after the inquire cycle. if inv is sampled asserted during an inquire cycle, the processor transitions the line (if found) to the invalid state, regardless of its previous state. the cache line invalidation operation is not visible on the bus. if inv is sampled negated during an inquire cycle, the processor transitions the line (if found) to the shared state. in figure 53 the processor samples inv asserted during the inquire cycle. in a hold-initiated inquire cycle, the system logic can negate hold off the same clock edge on which eads# is sampled asserted. the processor drives hit# and hitm# on the clock edge after the clock edge on which eads# is sampled asserted.
chapter 6 bus cycles 141 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 53. hold-initiated inquire hit to modified line burst memory read inquire writeback cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# eads# hit# hitm# d[63:0] ken# brdy# hold hlda inv
142 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information ahold-initiated inquire miss ahold can be asserted by the system to initiate one or more inquire cycles. to allow the system to drive the address bus during an inquire cycle, the processor floats a[31:3] and ap off the clock edge on which ahold is sampled asserted. the data bus and all other control and status signals remain under the control of the processor and are not floated. this functionality allows a bus cycle in progress when ahold is sampled asserted to continue to completion. the processor resumes driving the address bus off the clock edge on which ahold is sampled negated. in figure 54 on page 143, the processor samples ahold asserted during the memory burst read cycle, and it floats the address bus off the same clock edge on which it samples ahold asserted. while the processor still controls the bus, it completes the current cycle until the last expected brdy# is sampled asserted. the system logic drives eads# with an inquire address on a[31:5] during an inquire cycle. the processor samples eads# asserted and compares the inquire address to its tag address in both the instruction and data caches. in figure 54, the inquire address misses the tag address in the processor (both hit# and hitm# are negated). therefore, the processor proceeds to the next cycle when it samples ahold negated. (the processor can drive a new cycle by asserting ads# off the same clock edge that it samples ahold negated.) for an ahold-initiated inquire cycle to be recognized, the processor must sample ahold asserted for at least two consecutive clocks before it samples eads# asserted. if the processor detects an address parity error during an inquire cycle, apchk# is asserted for one clock. the system logic must respond appropriately to the assertion of this signal.
chapter 6 bus cycles 143 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 54. ahold-initiated inquire miss read inquire clk a[31:3] be[7:0]# ap apchk# ads# hit# hitm# d[63:0] ken# brdy# ahold eads# inv
144 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information ahold-initiated inquire hit to shared or exclusive line in figure 55 on page 145, the processor asserts hit# and negates hitm# off the clock edge after the clock edge on which eads# is sampled asserted, indicating the current inquire cycle hits either a shared or exclusive line. (hit# is driven in the same state until the next inquire cycle.) the processor samples inv asserted during the inquire cycle and transitions the line to the invalid state regardless of its previous state. during an ahold-initiated inquire cycle, the processor samples ahold on every clock edge until it is negated. in figure 55, the processor asserts ads# off the same clock on which ahold is sampled negated. if the inquire cycle hits a modified line, the processor performs a writeback cycle before it drives a new bus cycle. the next section describes the ahold-initiated inquire cycle that hits a modified line.
chapter 6 bus cycles 145 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 55. ahold-initiated inquire hit to shared or exclusive line burst memory read inquire clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# hit# hitm# d[63:0] ken# brdy# ahold inv eads#
146 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information ahold-initiated inquire hit to modified line figure 56 on page 147 shows an ahold-initiated inquire cycle that hits a modified line. during the inquire cycle in this example, the processor asserts both hit# and hitm# on the clock edge after the clock edge that it samples eads# asserted. this condition indicates that the cache line exists in the processors data cache in the modified state. if the inquire cycle hits a modified line, the processor performs a writeback cycle immediately after the inquire cycle to update the modified cache line to shared memory (normally level-two cache or dram). in figure 56, the system logic holds ahold asserted throughout the inquire cycle and the processor writeback cycle. in this case, the processor is not driving the address bus during the writeback cycle because ahold is sampled asserted. the system logic writes the data to memory by using its latched copy of the inquire cycle address. if the processor samples ahold negated before it performs the writeback cycle, it drives the writeback cycle by using the address (a[31:5]) that it latched during the inquire cycle. if inv is sampled asserted during an inquire cycle, the processor transitions the line (if found) to the invalid state, regardless of its previous state (the cache invalidation operation is not visible on the bus). if inv is sampled negated during an inquire cycle, the processor transitions the line (if found) to the shared state. in either case, if the line is found in the modified state, the processor writes it back to memory before changing its state. figure 56 shows that the processor samples inv asserted during the inquire cycle and invalidates the cache line after the inquire cycle.
chapter 6 bus cycles 147 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 56. ahold-initiated inquire hit to modified line burst memory read inquire writeback clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# hit# hitm# d[63:0] ken# brdy# ahold eads# inv
148 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information ahold restriction when the system logic drives an ahold-initiated inquire cycle, it must assert ahold for at least two clocks before it asserts eads#. this requirement guarantees the processor recognizes and responds to the inquire cycle properly. the processors 32 address bus drivers turn on almost immediately after ahold is sampled negated. if the processor switches the data bus (d[63:0] and dp[7:0]) during a write cycle off the same clock edge that switches the address bus (a[31:3] and ap), the processor switches 102 drivers simultaneously, which can lead to ground-bounce spikes. therefore, before negating ahold the following restrictions must be observed by the system logic: n when the system logic negates ahold during a write cycle, it must ensure that ahold is not sampled negated on the clock edge on which brdy# is sampled asserted (see figure 57 on page 149). n when the system logic negates ahold during a writeback cycle, it must ensure that ahold is not sampled negated on the clock edge on which ads# is negated (see figure 57). n when a write cycle is pipelined into a read cycle, ahold must not be sampled negated on the clock edge after the clock edge on which the last brdy# of the read cycle is sampled asserted to avoid the processor simultaneously driving the data bus (for the pending write cycle) and the address bus off this same clock edge.
chapter 6 bus cycles 149 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 57. ahold restriction the system must ensure that ahold is not sampled negated on the clock edge that ads # is negated. legal ahold negation during write cycle illegal ahold negation during write cycle clk ads# w/r# hitm# eads# d[63:0] brdy# ahold the system must ensure that ahold is not sampled negated on the clock edge on which brdy # is sample d asserted .
150 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information bus backoff (boff#) boff# provides the fastest response among bus-hold inputs. either the system logic or another bus master can assert boff# to gain control of the bus immediately. boff# is also used to resolve potential deadlock problems that arise as a result of inquire cycles. the processor samples boff# on every clock edge. if boff# is sampled asserted, the processor unconditionally aborts any cycles in progress and transitions to a bus hold state. ( see boff# (backoff) on page 87.) figure 58 on page 151 shows a read cycle that is aborted when the processor samples boff# asserted even though brdy# is sampled asserted on the same clock edge. the read cycle is restarted after boff# is sampled negated (ken# must be in the same state during the restarted cycle as its state during the aborted cycle). during a boff#-initiated inquire cycle that hits a shared or exclusive line, the processor samples boff# negated and restarts any bus cycle that was aborted when boff# was asserted. if a boff#-initiated inquire cycle hits a modified line, the processor performs a writeback cycle before it restarts the aborted cycle. if the processor samples boff# asserted on the same clock edge that it asserts ads#, ads# is floated but the system logic may erroneously interpret ads# as asserted. in this case, the system logic must properly interpret the state of ads# when boff# is negated.
chapter 6 bus cycles 151 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 58. boff# timing read back off cycle restart read cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# boff# d[63:0] brdy#
152 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information locked cycles the processor asserts lock# during a sequence of bus cycles to ensure the cycles are completed without allowing other bus masters to intervene. locked operations can consist of two to five cycles. lock# is asserted during the following operations: n an interrupt acknowledge sequence n descriptor table accesses n page directory and page table accesses n xchg instruction n an instruction with an allowable lock prefix in order to ensure that locked operations appear on the bus and are visible to the entire system, any data operands addressed during a locked cycle that reside in the processors cache are flushed and invalidated from the cache prior to the locked operation. if the cache line is in the modified state, it is written back and invalidated prior to the locked operation. likewise, any data read during a locked operation is not cached. the processor negates lock# for at least one clock between consecutive sequences of locked operations to allow the system logic to arbitrate for the bus. the processor asserts scyc during misaligned locked transfers on the d[63:0] data bus. the processor generates additional bus cycles to complete the transfer of misaligned data. basic locked operation figure 59 on page 153 shows a pair of read-write bus cycles. it represents a typical read-modify-write locked operation. the processor asserts lock# off the same clock edge that it asserts ads# of the first bus cycle in the locked operation and holds it asserted until the last expected brdy# of the last bus cycle in the locked operation is sampled asserted. (the processor negates lock# off the same clock edge.)
chapter 6 bus cycles 153 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 59. basic locked operation locked read cycle locked write cycle clk a[31:3] be[7:0]# ads# lock# m/io# d/c# w/r# d[63:0] brdy# addr data data data idle idle addr data data data idle idle addr scyc
154 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information locked operation with boff# intervention figure 60 on page 155 shows boff# asserted within a locked read-write pair of bus cycles. in this example, the processor asserts lock# with ads# to drive a locked memory read cycle followed by a locked memory write cycle. during the locked memory write cycle in this example, the processor samples boff# asserted. the processor immediately aborts the locked memory write cycle and floats all its bus-driving signals, including lock#. the system logic or another bus master can initiate an inquire cycle or drive a new bus cycle one clock edge after the clock edge on which boff# is sampled asserted. if the system logic drives a boff#-initiated inquire cycle and hits a modified line, the processor performs a writeback cycle before it restarts the locked cycle (the processor asserts lock# during the writeback cycle). in figure 60, the processor immediately restarts the aborted locked write cycle by driving the bus off the clock edge on which boff# is sampled negated. the system logic must ensure the processor results for interrupted and uninterrupted locked cycles are consistent. that is, the system logic must guarantee the memory accessed by the processor is not modified during the time another bus master controls the bus.
chapter 6 bus cycles 155 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 60. locked operation with boff# intervention locked read cycle aborted write cycle restart write cycle clk a[31:3] be[7:0]# ads# lock# m/io# d/c# w/r# boff# d[63:0] brdy#
156 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information interrupt acknowledge in response to recognizing the systems maskable interrupt (intr), the processor drives an interrupt acknowledge cycle at the next instruction boundary. during an interrupt acknowledge cycle, the processor drives a locked pair of read cycles as shown in figure 61 on page 157. the first read cycle is not functional, and the second read cycle returns the interrupt number on d[7:0] (00hCffh). table 23 shows the state of the signals during an interrupt acknowledge cycle. the system logic can drive intr either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. to ensure it is recognized, intr must remain asserted until an interrupt acknowledge sequence is complete. table 23. interrupt acknowledge operation definition processor outputs first bus cycle second bus cycle d/c# low low m/io# low low w/r# low low be[7:0]# efh feh (low byte enabled) a[31:3] 0000_0000h 0000_0000h d[63:0] (ignored) interrupt number expected from interrupt controller on d[7:0]
chapter 6 bus cycles 157 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 61. interrupt acknowledge operation interrupt acknowledge cycles interrupt number clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# lock# intr d[63:0] ken# brdy#
158 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 6.6 special bus cycles the amd-k6 processor drives special bus cycles that include stop grant, flush acknowledge, cache writeback invalidation, halt, cache invalidation, and shutdown cycles. during all special cycles, d/c# = 0, m/io# = 0, and w/r# = 1. be[7:0]# and a[31:3] are driven to differentiate among the special cycles, as shown in table 24. the system logic must return brdy# in response to all processor special cycles. basic special bus cycle figure 62 on page 159 shows a basic special bus cycle. the processor drives d/c# = 0, m/io# = 0, and w/r# = 1 off the same clock edge that it asserts ads#. in this example, be[7:0]# = fbh and a[31:3] = 0000_0000h, which indicates that the special cycle is a halt special cycle (see table 24). a halt special cycle is generated after the processor executes the hlt instruction. if the processor samples flush# asserted, it writes back any data cache lines that are in the modified state and invalidates all lines in the instruction and data cache. the processor then drives a flush acknowledge special cycle. if the processor executes a wbinvd instruction, it drives a writeback special cycle after the processor completes invalidating and writing back the cache lines. table 24. encodings for special bus cycles be[7:0]# a[4:3]* special bus cycle cause fbh 10b stop grant stpclk# sampled asserted efh 00b flush acknowledge flush# sampled asserted f7h 00b writeback wbinvd instruction fbh 00b halt hlt instruction fdh 00b flush invd,wbinvd instruction feh 00b shutdown triple fault note: * a[31:5] = 0
chapter 6 bus cycles 159 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 62. basic special bus cycle (halt cycle) halt cycle a[4:3] = 00b fbh clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# brdy#
16 0 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information shutdown cycle in figure 63, a shutdown (triple fault) occurs in the first half of the waveform, and a shutdown special cycle follows in the second half. the processor enters shutdown when an interrupt or exception occurs during the handling of a double fault (int 8), which amounts to a triple fault. when the processor encounters a triple fault, it stops its activity on the bus and generates the shutdown special bus cycle (be[7:0]# = feh). the system logic must assert nmi, init, reset, or smi# to get the processor out of the shutdown state. figure 63. shutdown cycle shutdown occurs (triple fault) shutdown special cycle clk a[31:3] be[7:0]# ads# lock# m/io# d/c# w/r# d[63:0] ken# brdy# a[4:3] = 00b feh
chapter 6 bus cycles 161 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information stop grant and stop clock states figure 64 on page 162 and figure 65 on page 163 show the processor transition from normal execution to the stop grant state, then to the stop clock state, back to the stop grant state, and finally back to normal execution. the series of transitions begins when the processor samples stpclk# asserted. on recognizing a stpclk# interrupt at the next instruction retirement boundary, the processor performs the following actions, in the order shown: 1. its instruction pipelines are flushed 2. all pending and in-progress bus cycles are completed 3. the stpclk# assertion is acknowledged by executing a stop grant special bus cycle 4. its internal clock is stopped after brdy# of the stop grant special bus cycle is sampled asserted and after ewbe# is sampled asserted 5. the stop clock state is entered if the system logic stops the bus clock clk (optional) stpclk# is sampled as a level-sensitive input on every clock edge but is not recognized until the next instruction boundary. the system logic drives the signal either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. stpclk# must remain asserted until recognized, which is indicated by the completion of the stop grant special cycle.
162 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 64. stop grant and stop clock modes, part 1 stpclk# sampled asserted stop grant special cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# cache# stpclk# d[63:0] ken# brdy# stop clock a[4:3] = 10b fbh
chapter 6 bus cycles 163 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 65. stop grant and stop clock modes, part 2 stop grant state (re-entered after pll stabilization) stpclk# sampled normal stop clock clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# cache# stpclk# d[63:0] ken# brdy# negated
164 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information init-initiated transition from protected mode to real mode init is typically asserted in response to a bios interrupt that writes to an i/o port. this interrupt is often in response to a ctrl-alt-del keyboard input. the bios writes to a port (similar to port 64h in the keyboard controller) that asserts init. init is also used to support 80286 software that must return to real mode after accessing extended memory in protected mode. the assertion of init causes the processor to empty its pipelines, initialize most of its internal state, and branch to address ffff_fff0h the same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the mmx state, model-specific registers (msrs), the cd and nw bits of the cr0 register, the time stamp counter, and other specific internal resources. figure 66 on page 165 shows an example in which the operating system writes to an i/o port, causing the system logic to assert init. the sampling of init asserted starts an extended microcode sequence that terminates with a code fetch from ffff_fff0h, the reset location. init is sampled on every clock edge but is not recognized until the next instruction boundary. during an i/o write cycle, it must be sampled asserted a minimum of three clock edges before brdy# is sampled asserted if it is to be recognized on the boundary between the i/o write instruction and the following instruction. if init is asserted synchronously, it can be asserted for a minimum of one clock. if it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks.
chapter 6 bus cycles 165 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 66. init-initiated transition from protected mode to real mode code fetch ffff_fff0 init sampled asserted clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] ken# brdy# init
16 6 bus cycles chapter 6 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 7 power-on configuration and initialization 167 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 7 power-on configuration and initialization on power-on the system logic must reset the amd-k6 processor by asserting the reset signal. when the processor samples reset asserted, it immediately flushes and initializes all internal resources and its internal state, including its pipelines and caches, the floating-point state, the mmx state, and all registers. then the processor jumps to address ffff_fff0h to start instruction execution. 7.1 signals sampled during the falling transition of reset flush# flush# is sampled on the falling transition of reset to determine if the processor begins normal instruction execution or enters tri-state test mode. if flush# is high during the falling transition of reset, the processor unconditionally runs its built-in self test (bist), performs the normal reset functions, then jumps to address ffff_fff0h to start instruction execution. (see built-in self-test (bist) on page 203 for more details.) if flush# is low during the falling transition of reset, the processor enters tri-state test mode. (see tri-state test mode on page 204 and flush# (cache flush) on page 97 for more details.) bf[2:0] the internal operating frequency of the processor is determined by the state of the bus frequency signals bf[2:0] when they are sampled during the falling transition of reset. the frequency of the clk input signal is multiplied internally by a ratio defined by bf[2:0]. (see bf[2:0] (bus frequency) on page 86 for the processor-clock to bus-clock ratios.) brdyc# brdyc# is sampled on the falling transition of reset to configure the drive strength of a[20:3], ads#, hitm#, and w/r#. if brdyc# is low during the fall of reset, these outputs are configured using higher drive strengths than the standard strength. if brdyc# is high during the fall of reset, the standard strength is selected. (see brdyc# (burst ready copy) on page 89 for more details.)
16 8 power-on configuration and initialization chapter 7 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 7.2 reset requirements during the initial power-on reset of the processor, reset must remain asserted for a minimum of 1.0 ms after clk and v cc reach specification. ( see clk switching characteristics on page 241 for clock specifications. see electrical data on page 233 for v cc specifications.) during a warm reset while clk and v cc are within specification, reset must remain asserted for a minimum of 15 clocks prior to its negation. 7.3 state of processor after reset output signals table 25 shows the state of all processor outputs and bidirectional signals immediately after reset is sampled asserted. registers table 26 on page 169 shows the state of all architecture registers and model-specific registers (msrs) after the processor has completed its initialization due to the recognition of the assertion of reset. table 25. output signal state after reset signal state signal state a[31:3], ap floating hlda low ads#, adsc# high lock# high apchk# high m/io# low be[7:0]# floating pcd low breq low pchk# high cache# high pwt low d/c# low scyc low d[63:0], dp[7:0] floating smiact# high ferr# high tdo floating hit# high vcc2det low hitm# high w/r# low
chapter 7 power-on configuration and initialization 169 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information table 26. register state after reset register state (hex) notes gdtr base:0000_0000h limit:0 ffffh idtr base:0000_0000h limit:0 ffffh tr 0000h ldtr 0000h eip ffff_fff0h eflags 0000_0002h eax 0000_0000h 1 ebx 0000_0000h ecx 0000_0000h edx 0000_056xh 2 esi 0000_0000h edi 0000_0000h ebp 0000_0000h esp 0000_0000h cs f000h ss 0000h ds 0000h es 0000h fs 0000h gs 0000h fpu stack r7Cr0 0000_0000_0000_0000_0000h 3 fpu control word 0040h 3 fpu status word 0000h 3 fpu tag word 5555h 3 fpu instruction pointer 0000_0000_0000h 3 fpu data pointer 0000_0000_0000h 3 fpu opcode register 000_0000_0000b 3 cr0 6000_0010h 4 cr2 0000_0000h notes: 1. the contents of eax indicate if bist was successful. if eax = 0000_0000h, bist was successful. if eax is non-zero, bist failed. 2. edx contains the amd-k6 processor signature, where x indicates the processor stepping id. 3. the contents of these registers are preserved following the recognition of init. 4. the cd and nw bits of cr0 are preserved following the recognition of init.
170 power-on configuration and initialization chapter 7 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 7.4 state of processor after init the recognition of the assertion of init causes the processor to empty its pipelines, to initialize most of its internal state, and to branch to address ffff_fff0hthe same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the mmx state, msrs, and the cd and nw bits of the cr0 register. the edge-sensitive interrupts flush# and smi# are sampled and preserved during the init process and are handled accordingly after the initialization is complete. however, the processor resets any pending nmi interrupt upon sampling init asserted. init can be used as an accelerator for 80286 code that requires a reset to exit from protected mode back to real mode. cr3 0000_0000h cr4 0000_0000h dr7 0000_0400h dr6 ffff_0ff0h dr3 0000_0000h dr2 0000_0000h dr1 0000_0000h dr0 0000_0000h mcar 0000_0000_0000_0000h 3 mctr 0000_0000_0000_0000h 3 tr12 0000_0000_0000_0000h 3 tsc 0000_0000_0000_0000h 3 whcr 0000_0000_0000_0000h 3 table 26. register state after reset (continued) register state (hex) notes notes: 1. the contents of eax indicate if bist was successful. if eax = 0000_0000h, bist was successful. if eax is non-zero, bist failed. 2. edx contains the amd-k6 processor signature, where x indicates the processor stepping id. 3. the contents of these registers are preserved following the recognition of init. 4. the cd and nw bits of cr0 are preserved following the recognition of init.
chapter 8 cache organization 171 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 8 cache organization the following sections describe the basic architecture and resources of the amd-k6 processor internal caches. the performance of the amd-k6 processor is enhanced by a writeback level-one (l1) cache. the cache is organized as a separate 32-kbyte instruction cache and a 32-kbyte data cache, each with two-way set associativity (see figure 67). the cache line size is 32 bytes, and lines are prefetched from main memory using an efficient, pipelined burst transaction. as the instruction cache is filled, each instruction byte is analyzed for instruction boundaries using predecode logic. predecoding annotates each instruction byte with information that later enables the decoders to efficiently decode multiple instructions simultaneously. translation lookaside buffers (tlb) are also used to translate linear addresses to physical addresses. the instruction cache is associated with a 64-entry tlb while the data cache is associated with a 128-entry tlb. figure 67. cache organization processor core system bus interface unit 128-entry tlb 64-entry tlb state bit tag ram way 0 way 1 state bit tag ra 32-kbyte instruction cache 32-kbyte data cache pre-decode instruction cache mesi bits tag ram way 0 way 1 mesi bits tag ra
17 2 cache organization chapter 8 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information the processor cache design takes advantage of a sectored organization (see figure 68). each sector consists of 64 bytes configured as two 32-byte cache lines. the two cache lines of a sector share a common tag but have separate mesi (modified, exclusive, shared, invalid) bits that track the state of each cache line. instruction cache line data cache line note: instruction-cache lines have only two coherency states (valid or invalid) rather than the four mesi coherency states of data-cache lines. only two states are needed for the instruction cache because these lines are read-only. figure 68. cache sector organization 8.1 mesi states in the data cache the state of each line in the caches is tracked by the mesi bits. the coherency of these states or mesi bits is maintained by internal processor snoops and external inquiries by the system logic. the following four states are defined for the data cache: n modifie d this line has been modified and is different from main memory. n exclusive this line is not modified and is the same as main memory. if this line is written to, it becomes modified. n shared if a cache line is in the shared state it means that the same line can exist in more than one cache system. n invalid the information in this line is not valid. 8.2 predecode bits decoding x86 instructions is particularly difficult because the instructions vary in length, ranging from 1 to 15 bytes long. predecode logic supplies the predecode bits associated with each instruction byte. the predecode bits indicate the number tag address cache line 1 byte 31 predecode bits byte 30 predecode bits ........ ........ byte 0 predecode bits 1 mesi bit cache line 2 byte 31 predecode bits byte 30 predecode bits ........ ........ byte 0 predecode bits 1 mesi bit tag address cache line 1 byte 31 byte 30 ........ ........ byte 0 2 mesi bits cache line 2 byte 31 byte 30 ........ ........ byte 0 2 mesi bits
chapter 8 cache organization 17 3 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information of bytes to the start of the next x86 instruction. the predecode bits are passed with the instruction bytes to the decoders where they assist with parallel x86 instruction decoding. the predecode bits use memory separate from the 32-kbyte instruction cache. the predecode bits are stored in an extended instruction cache alongside each x86 instruction byte as shown in figure 68 on page 172. 8.3 cache operation the operating modes for the caches are configured by software using the not writethrough (nw) and cache disable (cd) bits of control register 0 (cr0 bits 29 and 30 respectively). these bits are used in all operating modes. when the cd and nw bits are both set to 0, the cache is fully enabled. this is the standard operating mode for the cache. if a read miss occurs when the processor reads from the cache, a line fill takes place. write hits to the cache are updated, while write misses and writes to shared lines cause external memory updates. note: a write allocate operation can modify the behavior of write misses to the cache. see write allocate on page 177. when cd is set to 0 and nw is set to 1, an invalid mode of operation exists that causes a general protection fault to occur. when cd is set to 1 (disabled) and nw is set to 0, the cache fill mechanism is disabled but the contents of the cache are still valid. the processor reads from the cache and, if a read miss occurs, no line fills take place. write hits to the cache are updated, while write misses and writes to shared lines cause external memory updates. when the cd and nw bits are both set to 1, the cache is fully disabled. even though the cache is disabled, the contents are not necessarily invalid. the processor reads from the cache and, if a read miss occurs, no line fills take place. if a write hit occurs, the cache is updated but an external memory update does not occur. if a data line is in the exclusive state during a write hit, the mesi bits are changed to the modified state. write misses access memory directly.
174 cache organization chapter 8 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information the operating system can control the cacheability of a page. the paging mechanism is controlled by cr3, the page directory entry (pde), and the page table entry (pte). within cr3, pde, and pte are page cache disable (pcd) and page writethrough (pwt) bits. the values of the pcd and pwt bits used in table 27 through table 29 are taken from either the pte or pde. for more information see the descriptions of pcd and pwt on pages 107 and 109, respectively. table 27 through table 29 describe the logic that determines the cacheability of a cycle and how that cacheability is affected by the pcd bits, the pwt bits, the pg bit of cr0, the cd bit of cr0, writeback cycles, the cache inhibit (ci) bit of test register 12 (tr12), and unlocked memory reads. table 27 describes how the pwt signal is driven based on the values of the pwt bits and the pg bit of cr0. table 28 describes how the pcd signal is driven based on the values of the cd bit of cr0, the pcd bits, and the pg bit of cr0. table 27. pwt signal generation pwt bit* pg bit of cr0 pwt signal 11high 01low 10low 00low note: * pwt is taken from pte or pde table 28. pcd signal generation cd bit of cr0 pcd bit* pg bit of cr0 pcd signal 1xxhigh 011high 001low 010low 000low note: * pcd is taken from pte or pde
chapter 8 cache organization 17 5 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information table 29 describes how the cache# signal is driven based on writeback cycles, the ci bit of tr12, unlocked memory reads, and the pcd signal. cache-related signals complete descriptions of the signals that control cacheability and cache coherency are given on the following pages: n cache# page 90 n eads#page 94 n flush#page 97 n hit#page 98 n hitm#page 98 n invpage 102 n ken#page 103 n pcdpage 107 n pwtpage 109 n wb/wt#page 116 8.4 cache disabling to completely disable all cache accesses, the cd and nw bits must be set to 1 and the cache must be completely flushed. there are two different methods for flushing the cache. the first method relies on the system logic and the second relies on software. table 29. cache# signal generation writeback cycle ci bit of tr12 unlocked memory reads pcd signal cache# 1x xxlow 01 1highhigh 00 1highhigh 01 0highhigh 00 0highhigh 01 1lowhigh 00 1lowlow 01 0lowhigh 00 0lowhigh
176 cache organization chapter 8 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information for the system logic to flush the cache, the processor must sample flush# asserted. in this method, the processor writes back any data cache lines that are in the modified state, invalidates all lines in the instruction and data caches, and then executes a flush acknowledge special cycle (see table 19 on page 119). software can use two different instructions to flush the cache. both the wbinvd and invd instructions cause all cache lines to be marked invalid. the wbinvd instruction causes all modified lines to first be written back to memory. the invd instruction invalidates all cache lines without writing modified lines back to memory. any area of system memory can be cached. however, the processor prevents caching of locked operations and tlb reads, the operating system can prevent caching of certain pages by setting the pcd and pwt bits in the pde or pte, and system logic can prevent caching of certain bus cycles by negating the ken# input signal with the first brdy# or na# of a cycle. 8.5 cache-line fills when the cpu needs to read memory, the processor drives a read cycle onto the bus. if the cycle is cacheable the cpu asserts cache#. the system logic also has control of the cacheability of bus cycles. if it determines the address is cacheable, system logic asserts the ken# signal and the appropriate value of wb/wt#. one of two events takes place next. if the cycle is not cacheable, a non-pipelined, single-transfer read takes place. the processor waits for the system logic to return the data and assert a single brdy# (see figure 45 on page 127). if the cycle is cacheable, the processor executes a 32-byte burst read cycle. the processor expects to sample brdy# asserted a total of four times for a burst read cycle to take place (see figure 47 on page 131). instruction-cache line fills initiate 32-byte transfers from memory (one burst cycle) on the bus. data-cache line fills also initiate 32-byte transfers on the bus. if the data-cache line being filled replaces a modified line, the prior contents of the line are copied to a 32-byte writeback (copyback) buffer in the bus interface unit while the new line is being read.
chapter 8 cache organization 17 7 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 8.6 cache-line replacements as programs execute and task switches occur, some cache lines eventually require replacement. instruction cache lines are replaced using a least recently used (lru) algorithm. if line replacement is required, lines are replaced when read cache misses occur. the data cache uses a slightly different approach to line replacement. if a miss occurs, and a replacement is required, lines are replaced by using a least recently allocated (lra) algorithm. two forms of cache misses and associated cache fills can take placea sector replacement and a cache line replacement. in the case of a sector replacement, the miss is due to a tag mismatch, in which case the required cache line is filled from external memory, and the cache line within the sector that was not required is marked as invalid. in the case of a cache line replacement, the address matches the tag, but the requested cache line is marked as invalid. the required cache line is filled from external memory, and the cache line within the sector that is not required remains in the same cache state. 8.7 write allocate write allocate, if enabled, occurs when the processor has a pending memory write cycle to a cacheable line and the line does not currently reside in the l1 data cache. in this case, the processor performs a burst read cycle to fetch the data-cache line addressed by the pending write cycle. the data associated with the pending write cycle is merged with the recently-allocated data-cache line and stored in the processors l1 data cache. the final mesi state of the cache line depends on the state of the wb/wt# and pwt signals during the burst read cycle and the subsequent cache write hit (see table 30 on page 182 to determine the cache-line states and the access types following a cache read miss and cache write hit). during write allocates, a 32-byte burst read cycle is executed in place of a non-burst write cycle. while the burst read cycle generally takes longer to execute than the write cycle, performance gains are realized on subsequent write cycle hits
178 cache organization chapter 8 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information to the write-allocated cache line. due to the nature of software, memory accesses tend to occur in proximity of each other (principle of locality). the likelihood of additional write hits to the write-allocated cache line is high. the following is a description of three mechanisms by which the amd-k6 processor performs write allocations. a write allocate is performed when any one or more of these mechanisms indicates that a pending write is to a cacheable area of memory. write to a cacheable page every time the processor performs a cache line fill, the address of the page in which the cache line resides is saved in the cacheability control register (ccr). the page address of subsequent write cycles is compared with the page address stored in the ccr. if the two addresses are equal, then the processor performs a write allocate because the page has already been determined to be cacheable. when the processor performs a cache line fill from a different page than the address saved in the ccr, the ccr is updated with the new page address. write to a sector if the address of a pending write cycle matches the tag address of a valid cache sector, but the addressed cache line within the sector is marked invalid (a sector hit but a cache line miss), then the processor performs a write allocate. the pending write cycle is determined to be cacheable because the sector hit indicates the presence of at least one valid cache line in the sector. the two cache lines within a sector are guaranteed by design to be within the same page. write allocate limit the write handling control register (whcr) is a msr that contains three fields the wcde bit, the write allocate enable limit (waelim) field, and the write allocate enable 15-to-16-mbyte (wae15m) bit (see figure 69 on page 179). for proper functionality, always program the wcde bit to 0.
chapter 8 cache organization 179 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 69. write handling control register (whcr) the waelim field is 7 bits wide. this field, multiplied by 4 mbytes, defines an upper memory limit. any pending write cycle that addresses memory below this limit causes the processor to perform a write allocate. write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanismswrite to a cacheable page and write to a sector. the maximum value of this memory limit is ((2 7 C 1) 4 mbytes) = 508 mbytes. when all the bits in this field are set to 0, all memory is above this limit and this mechanism for allowing write allocate is effectively disabled. the write allocate enable 15-to-16-mbyte (wae15m) bit is used to enable write allocations for the memory write cycles that address the 1 mbyte of memory between 15 mbytes and 16 mbytes. this bit must be set to 1 to allow write allocate in this memory area. this bit is provided to account for a small number of uncommon memory-mapped i/o adapters that use this particular memory address space. if the system contains one of these peripherals, the bit should be set to 0. the wae15m bit is ignored if the value in the waelim field is set to less than 16 mbytes. by definition a write allocate is never performed in the memory area between 640 kbytes and 1 mbyte unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanismswrite to a cacheable page and write to a sector. it is not considered safe to perform 71 0 63 reserved waelim 8 0 note : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits wcde always program to 0 8 waelim write allocate enable limit 7C1 wae15m write allocate enable 15-to-16-mbyte 0 9
18 0 cache organization chapter 8 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because it is considered a non-cacheable region of memory. figure 70 shows the logic flow for all the mechanisms involved with write allocate for memory bus cycles. the left side of the diagram (the text) describes the conditions that need to be true in order for the value of that line to be a 1. items 1 to 3 of the diagram are related to general cache operation and items 4 to 11 are related to the write allocate mechanisms. for more information about write allocate, see the implementation of write allocate in the k86? processors application note , order# 21326. figure 70. write allocate logic mechanisms and conditions descriptions of the logic mechanisms and conditions 1. cd bit of cr0 when the cache disable (cd) bit within control register 0 (cr0) is set to 1, the cache fill mechanism for both reads and writes is disabled, therefore write allocate does not occur. 2. pcd signal when the pcd (page cache disable) signal is driven high, caching for that page is disabled even if ken# is sampled asserted, therefore write allocate does not occur. 3. ci bit of tr12 when the cache inhibit bit of test register 12 is set to 1, the l1 caches are disabled, therefore write allocate does not occur. 4. write to a cacheable page (ccr) a write allocate is performed if the processor knows that a page is cacheable. the ccr is used to store the page address of the last cache fill for a read miss. see write to a cacheable page on page 178 for a detailed description of this condition. 1) cd bit of cr0. perform write allocate 3) ci bit of tr12 2) pcd signal 4) write to cacheable page (ccr) 5) write to a sector 8) between 640 kbytes and 1 mbyte 7) less than limit (waelim) 9) between 15C16 mbytes 10) write allocate enable 15C16 mbyte (wae15m) 6) wcde bit
chapter 8 cache organization 181 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 5. write to a sector a write allocate is performed if the address of a pending write cycle matches the tag address of a valid cache sector but the addressed cache line within the sector is invalid. see write to a sector on page 178 for a detailed description of this condition. 6. wcde bit for proper functionality, always program bit 8 of whcr to 0. 7. less than limit (waelim) the write allocate limit mechanism determines if the memory area being addressed is less than the limit set in the waelim field of whcr. if the address is less than the limit, write allocate for that memory address is performed as long as conditions 9 and 10 do not prevent write allocate. 8. between 640 kbytes and 1 mbyte write allocate is not performed in the memory area between 640 kbytes and 1 mbyte. it is not considered safe to perform write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because this area of memory is considered a non-cacheable region of memory. 9. between 15C16 mbytes if the address of a pending write cycle is in the 1 mbyte of memory between 15 mbytes and 16 mbytes, and the wae15m bit is set to 1, write allocate for this cycle is enabled. 10. write allocate enable 15C16 mbytes (wae15m) this condition is associated with the write allocate limit mechanism and affects write allocate only if the limit specified by the waelim field is greater than or equal to 16 mbytes. if the memory address is between 15 mbytes and 16 mbytes, and the wae15m bit in the whcr is set to 0, write allocate for this cycle is disabled. 8.8 prefetching the amd-k6 processor performs instruction cache prefetching for sector replacements only as opposed to cache-line replacements. the cache prefetching results in the filling of the required cache line first, and a prefetch of the second cache line making up the other half of the sector. furthermore, the prefetch of the second cache line is initiated only in the forward directionthat is, only if the requested cache line is the first position within the sector. from the perspective of the external
182 cache organization chapter 8 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information bus, the two cache-line fills typically appear as two 32-byte burst read cycles occurring back-to-back or, if allowed, as pipelined cycles. the burst read cycles do not occur back-to-back (wait states occur) if the processor is not ready to start a new cycle, if higher priority data read or write requests exist, or if na# (next address) was sampled negated. wait states can also exist between burst cycles if the processor samples ahold or boff# asserted. 8.9 cache states table 30 shows all the possible cache-line states before and after program-generated accesses to individual cache lines. the table includes the correspondence between mesi states and writethrough or writeback states for lines in the data cache. table 30. data cache states for read and write accesses type cache state before access access type 1 cache state after access mesi state writeback writethrough state cache read read miss invalid single read invalid C invalid burst read 2 (cacheable) shared or exclusive 3 writethrough or writeback 3 read hit shared C shared writethrough exclusive C exclusive writeback modified C modified writeback cache write write miss invalid single write 4 invalid C write hit shared cache update and single write shared or exclusive 3 writethrough or writeback 3 exclusive or modified cache update modified writeback notes: 1. single read, single write, cache update, and writethrough = 1 to 8 bytes. line fill = 32-byte burst read. 2. if cache# is driven low and ken# is sampled asserted. 3. if pwt is driven low and wb/wt# is sampled high, the line is cached in the exclusive (writeback) state. 4. a write cycle occurs only if the write allocate conditions as specified in write allocate on page 177 are not met. C not applicable or none.
chapter 8 cache organization 183 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 8.10 cache coherency different ways exist to maintain coherency between the system memory and cache memories. inquire cycles, internal snoops, flush#, wbinvd, invd, and line replacements all prevent inconsistencies between memories. inquire cycles inquire cycles are bus cycles initiated by system logic. these inquiries ensure coherency between the caches and main memory. in systems with multiple caching masters, system logic maintains cache coherency by driving inquire cycles to the processor. system logic initiates inquire cycles by asserting ahold, boff#, or hold to obtain control of the address bus and then driving eads#, inv (optional), and an inquire address (a[31:5]). this type of bus cycle causes the processor to compare the tags for both its instruction and data caches with the inquire address. if there is a hit to a shared or exclusive line in the data cache or a valid line in the instruction cache, the processor asserts hit#. if the compare hits a modified line in the data cache, the processor asserts hit# and hitm#. if hitm# is asserted, the processor writes the modified line back to memory. if inv was sampled asserted with eads#, a hit invalidates the line. if inv was sampled negated with eads#, a hit leaves the line in the shared state or transitions it from the exclusive or modified to shared state. internal snooping internal snooping is initiated by the processor (rather than system logic) during certain cache accesses. it is used to maintain coherency between the l1 instruction and data caches. the processor automatically snoops its instruction cache during read or write misses to its data cache, and it snoops its data cache during read misses to its instruction cache. table 31 on page 185 summarizes the actions taken during this internal snooping. if an internal snoop hits its target, the processor does the following: n data cache snoop during an instruction-cache read miss if modified, the line in the data cache is written back to memory. regardless of its state, the data-cache line is invalidated and the instruction cache performs a burst cycle read from memory.
184 cache organization chapter 8 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information n instruction cache snoop during a data cache miss the line in the instruction cache is marked invalid, and the data-cache read or write is performed from memory. flush# in response to sampling flush# asserted, the processor writes back any data cache lines that are in the modified state and then marks all lines in the instruction and data caches as invalid. wbinvd and invd these x86 instructions cause all cache lines to be marked as invalid. wbinvd writes back modified lines before marking all cache lines invalid. invd does not write back modified lines. cache-line replacement replacing lines in the instruction or data cache, according to the line replacement algorithms described in cache-line fills on page 176, ensures coherency between main memory and the caches. table 31 on page 185 shows all possible cache-line states before and after cache snoop or invalidation operations performed with inquire cycles. this table shows all of the conditions for writethroughs and writebacks to memory.
chapter 8 cache organization 185 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information table 31. cache states for inquiries, snoops, invalidation, and replacement type of operation cache state before operation memory access cache state after operation mesi state writeback writethrough state inquire cycle shared or exclusive C inv=0 shared writethrough inv=1 invalid invalid modified burst write (writeback) inv=0 shared writethrough inv=1 invalid invalid internal snoop shared or exclusive C invalid invalid modified burst write (writeback) flush# signal shared or exclusive C invalid invalid modified burst write (writeback) wbinvd instruction shared or exclusive C invalid invalid modified burst write (writeback) invd instruction C C invalid invalid cache-line replacement shared or exclusive C see table 30 modified burst write (writeback) notes: all writebacks are 32-byte burst write cycles. C not applicable or none.
18 6 cache organization chapter 8 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information cache snooping table 32 shows the conditions under which snooping occurs in the amd-k6 processor and the resources that are snooped. table 32. snoop action type of event type of access snooping action instruction cache data cache inquire cycle system logic yes 1 yes 1 internal snoop instruction cache read miss C yes 2 read hit Cno data cache read miss yes 3 C read hit no C write miss yes 3 C write hit no C notes: 1. the processors response to an inquire cycle depends on the state of the inv input signal and the state of the cache line as follows: for the instruction cache, if inv is sampled negated, the line remains invalid or valid, but if inv is sampled asserted, the line is invalidated. for the data cache, if inv is sampled negated, valid lines remain in or transition to the shared state, a modified data cache line is written back before the line is marked shared (with hitm# asserted), and invalid lines remain invalid. for the data cache, if inv is sampled asserted, the line is marked invalid. modified lines are written back before invalidation. 2. if an internal snoop hits a modified line in the data cache, the line is written back and invalidated. then the instruction cache performs a burst read from memory. 3. if an internal snoop hits a line in the instruction cache, the instruction cache line is invalidated and the data-cache read or write is performed from memory. C not applicable.
chapter 8 cache organization 187 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 8.11 writethrough vs. writeback coherency states the terms writethrough and writeback apply to two related concepts in a read-write cache like the amd-k6 processor l1 data cache. the following conditions apply to both the writethrough and writeback modes: n memory writes a relationship exists between external memory writes and their concurrence with cache updates: ? an external memory write that occurs concurrently with a cache update to the same location is a writethrough. writethroughs are driven as single cycles on the bus. ? an external memory write that occurs after the processor has modified a cache line is a writeback. writebacks are driven as burst cycles on the bus. n coherency state a relationship exists between mesi coherency states and writethrough-writeback coherency states of lines in the cache as follows: ? shared mesi lines are in the writethrough state. ? modified and exclusive mesi lines are in the writeback state. 8.12 a20m# masking of cache accesses although the processor samples a20m# as a level-sensitive input on every clock edge, it should only be asserted in real mode. the cpu applies the a20m# masking to its tags, through which all programs access the caches. therefore, assertion of a20m# affects all addresses (cache and external memory), including the following: n cache-line fills (caused by read misses) n cache writethroughs (caused by write misses or write hits to lines in the shared state) however, a20m# does not mask writebacks or invalidations caused by the following actions: n internal snoops n inquire cycles n the flush# signal n the wbinvd instruction
18 8 cache organization chapter 8 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 9 floating-point and multimedia execution units 189 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 9 floating-point and multimedia execution units 9.1 floating-point execution unit the amd-k6 processor contains an ieee 754-compatible and 854-compatible floating-point execution unit designed to accelerate the performance of software that utilizes the x86 floating-point instruction set. floating-point software is typically written to manipulate numbers that are very large or very small, that require a high degree of precision, or that result from complex mathematical operations such as transcendentals. applications that take advantage of floating-point operations include geometric calculations for graphics acceleration, scientific, statistical, and engineering applications, and business applications that use large amounts of high-precision data. the high-performance floating-point execution unit contains an adder unit, a multiplier unit, and a divide/square root unit. these low-latency units can execute floating-point instructions in as few as two processor clocks. to increase performance, the processor is designed to simultaneously decode most floating-point instructions with most short-decodeable instructions. see software environment on page 21 for a description of the floating-point data types, registers, and instructions. handling floating-point exceptions the amd-k6 processor provides the following two types of exception handling for floating-point exceptions: n if the numeric error (ne) bit in cr0 is set to 1, the processor invokes the interrupt 10h handler. in this manner, the floating-point exception is completely handled by software. n if the ne bit in cr0 is set to 0, the processor requires external logic to generate an interrupt on the intr signal in order to handle the exception. external logic support of floating-point exceptions the processor provides the ferr# (floating-point error) and ignne# (ignore numeric error) signals to allow the external logic to generate the interrupt in a manner consistent with ibm-compatible pc/at systems. the assertion of ferr# indicates the occurrence of an unmasked floating-point exception resulting from the execution of a floating-point
19 0 floating-point and multimedia execution units chapter 9 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information instruction. ignne# is used by the external hardware to control the effect of an unmasked floating-point exception. under certain circumstances, if ignne# is sampled asserted, the processor ignores the floating-point exception. figure 71 illustrates an implementation of external logic for supporting floating-point exceptions. the following example explains the operation of the external logic in figure 71: as the result of a floating-point exception, the processor asserts ferr#. the assertion of ferr# and the sampling of ignne# negated indicates the processor has stopped instruction execution and is waiting for an interrupt. the assertion of ferr# leads to the assertion of intr by the interrupt controller. the processor acknowledges the interrupt and jumps to the corresponding interrupt service routine in which an i/o write cycle to address port f0h leads to the assertion of ignne#. when ignne# is sampled asserted, the processor ignores the floating-point exception and continues instruction execution. when the processor negates ferr#, the external logic negates ignne#. see ferr# (floating-point error) on page 96 and ignne# (ignore numeric exception) on page 100 for more details. figure 71. external logic for supporting floating-point exceptions ferr# flip-flop clock q data q clear irq13 interrupt controller i/o address port f0h amd-k6 ? processor ferr# intr ignne# reset 1 ignne# flip-flop clock q data q clear
chapter 9 floating-point and multimedia execution units 191 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 9.2 multimedia execution unit the multimedia execution unit of the amd-k6 processor is designed to accelerate the performance of software written using the industry-standard mmx instructions. applications that can take advantage of the mmx instructions include graphics, video and audio compression and decompression, speech recognition, and telephony applications. the multimedia execution unit can execute mmx instructions in a single processor clock. to increase performance, the processor is designed to simultaneously decode all mmx instructions with most other instructions. for more information on mmx instructions, refer to amd-k6 ? processor multimedia technology , order# 20726. 9.3 floating-point and mmx? instruction compatibility registers the eight 64-bit mmx registers are mapped on the floating-point stack. this enables backward compatibility with all existing software. for example, the register saving event that is performed by operating systems during task switching requires no changes to the operating system. the same support provided in an operating systems interrupt 7 handler (device not available) for saving and restoring the floating-point registers also supports saving and restoring the mmx registers. exceptions there are no new exceptions defined for supporting the mmx instructions. all exceptions that occur while decoding or executing an mmx instruction are handled in existing exception handlers without modification. ferr# and ignne# mmx instructions do not generate floating-point exceptions. however, if an unmasked floating-point exception is pending, the processor asserts ferr# at the instruction boundary of the next floating-point instruction, mmx instruction, or wait instruction. the sampling of ignne# asserted only affects processor operation during the execution of an error-sensitive floating-point instruction, mmx instruction, or wait instruction when the ne bit in cr0 is set to 0.
192 floating-point and multimedia execution units chapter 9 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 10 system management mode (smm) 193 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 10 system management mode (smm) 10.1 overview smm is an alternate operating mode entered by way of a system management interrupt (smi#) and handled by an interrupt service routine. smm is designed for system control activities such as power management. these activities appear transparent to conventional operating systems like dos and windows. smm is primarily targeted for use by the basic input output system (bios) and specialized low-level device drivers. the code and data for smm are stored in the smm memory area, which is isolated from main memory. the processor enters smm by the system logics assertion of the smi# interrupt and the processors acknowledgment by the assertion of smiact#. at this point the processor saves its state into the smm memory state-save area and jumps to the smm service routine. the processor returns from smm when it executes the rsm (resume) instruction from within the smm service routine. subsequently, the processor restores its state from the smm save area, negates smiact#, and resumes execution with the instruction following the point where it entered smm. the following sections summarize the smm state-save area, entry into and exit from smm, exceptions and interrupts in smm, memory allocation and addressing in smm, and the smi# and smiact# signals. 10.2 smm operating mode and default register values the software environment within smm has the following characteristics: n addressing and operation in real mode n 4-gbyte segment limits n default 16-bit operand, address, and stack sizes, although instruction prefixes can override these defaults n control transfers that do not override the default operand size truncate the eip to 16 bits
194 system management mode (smm) chapter 10 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information n far jumps or calls cannot transfer control to a segment with a base address requiring more than 20 bits, as in real mode segment-base addressing n a20m# is masked n interrupt vectors use the real-mode interrupt vector table n the if flag in eflags is cleared (intr not recognized) n the tf flag in eflags is cleared n the nmi and init interrupts are disabled n debug register dr7 is cleared (debug traps disabled) figure 72 on page 195 shows the default map of the smm memory area. it consists of a 64-kbyte area, between 0003_0000h and 0003_ffffh, of which the top 32 kbytes (0003_8000h to 0003_ffffh) must be populated with ram. the default code-segment (cs) base address for the area called the smm base addressis at 0003_0000h. the top 512 bytes (0003_fe00h to 0003_ffffh) contain a fill-down smm state-save area. the default entry point for the smm service routine is 0003_8000h.
chapter 10 system management mode (smm) 195 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 72. smm memory table 33 shows the initial state of registers when entering smm. smm state-save area smm base address (cs) service routine entry point fill down smm service routine 32-kbyte minimum ram 0003_8000h 0003_fe00h 0003_ffffh 0003_0000h table 33. initial state of registers in smm registers smm initial state general purpose registers unmodified eflags 0000_0002h cr0 pe, em, ts, and pg are cleared (bits 0, 2, 3, and 31). the other bits are unmodified. dr7 0000_0400h gdtr, ldtr, idtr, tssr, dr6 unmodified eip 0000_8000h cs 0003_0000h ds, es, fs, gs, ss 0000_0000h
19 6 system management mode (smm) chapter 10 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 10.3 smm state-save area when the processor acknowledges an smi# interrupt by asserting smiact#, it saves its state in a 512-byte smm state-save area shown in table 34. the save begins at the top of the smm memory area (smm base address + ffffh) and fills down to smm base address + fe00h. table 34 shows the offsets in the smm state-save area relative to the smm base address. the smm service routine can alter any of the read/write values in the state-save area. table 34. smm state-save area map address offset contents saved fffch cr0 fff8h cr3 fff4h eflags fff0h eip ffech edi ffe8h esi ffe4h ebp ffe0h esp ffdch ebx ffd8h edx ffd4h ecx ffd0h eax ffcch dr6 ffc8h dr7 ffc4h tr ffc0h ldtr base ffbch gs ffb8h fs ffb4h ds ffb0h ss ffach cs ffa8h es notes: no data dump at that address * only contains information if smi# is asserted during a valid i/o bus cycle.
chapter 10 system management mode (smm) 197 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information ffa4h i/o trap dword ffa0h ff9ch i/o trap eip* ff98h ff94h ff90h idt base ff8ch idt limit ff88h gdt base ff84h gdt limit ff80h tss attr ff7ch tss base ff78h tss limit ff74h ff70h ldt high ff6ch ldt low ff68h gs attr ff64h gs base ff60h gs limit ff5ch fs attr ff58h fs base ff54h fs limit ff50h ds attr ff4ch ds base ff48h ds limit ff44h ss attr ff40h ss base ff3ch ss limit ff38h cs attr ff34h cs base ff30h cs limit ff2ch es attr table 34. smm state-save area map (continued) address offset contents saved notes: no data dump at that address * only contains information if smi# is asserted during a valid i/o bus cycle.
19 8 system management mode (smm) chapter 10 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 10.4 smm revision identifier the smm revision identifier at offset fefch in the smm state-save area specifies the version of smm and the extensions that are available on the processor. the smm revision identifier fields are as follows: n bits 31C18 reserved n bit 17 smm base address relocation (1 = enabled) n bit 16 i/o trap restart (1 = enabled) n bits 15C0 smm revision level for the amd-k6 processor = 0002h table 35 on page 199 shows the format of the smm revision identifier. ff28h es base ff24h es limit ff20h ff1ch ff18h ff14h cr2 ff10h cr4 ff0ch i/o restart esi* ff08h i/o restart ecx* ff04h i/o restart edi* ff02h halt restart slot ff00h i/o trap restart slot fefch smm revid fef8h smm base fef7hCfe00h table 34. smm state-save area map (continued) address offset contents saved notes: no data dump at that address * only contains information if smi# is asserted during a valid i/o bus cycle.
chapter 10 system management mode (smm) 199 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 10.5 smm base address during reset, the processor sets the base address of the code-segment (cs) for the smm memory areathe smm base addressto its default, 0003_0000h. the smm base address at offset fef8h in the smm state-save area can be changed by the smm service routine to any address that is aligned to a 32-kbyte boundary. (locations not aligned to a 32-kbyte boundary cause the processor to enter the shutdown state when executing the rsm instruction.) in some operating environments it may be desirable to relocate the 64-kbyte smm memory area to a high memory area in order to provide more low memory for legacy software. during system initialization, the base of the 64-kbyte smm memory area is relocated by the bios. to relocate the smm base address, the system enters the smm handler at the default address. this handler changes the smm base address location in the smm state-save area, copies the smm handler to the new location, and exits smm. the next time smm is entered, the processor saves its state at the new base address. this new address is used for every smm entry until the smm base address in the smm state-save area is changed or a hardware reset occurs. 10.6 halt restart slot during entry into smm, the halt restart slot at offset ff02h in the smm state-save area indicates if smm was entered from the halt state. before returning from smm, the halt restart slot (offset ff02h) can be written to by the smm service routine to specify whether the return from smm takes the processor back to the halt state or to the next instruction after the hlt instruction. table 35. smm revision identifier 31C18 17 16 15C0 reserved smm base relocation i/o trap extension smm revision level 0 1 1 0002h
200 system management mode (smm) chapter 10 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information upon entry into smm, the halt restart slot is defined as follows: n bits 15C1 reserved n bit 0 point of entry to smm: 1 = entered from halt state 0 = not entered from halt state after entry into the smi handler and before returning from smm, the halt restart slot can be written using the following definition: n bits 15C1 reserved n bit 0 point of return when exiting from smm: 1 = return to halt state 0 = return to next instruction after the hlt instruction if the return from smm takes the processor back to the halt state, the hlt instruction is not re-executed, but the halt special bus cycle is driven on the bus after the return. 10.7 i/o trap dword if the assertion of smi# is recognized during the execution of an i/o instruction, the i/o trap dword at offset ffa4h in the smm state-save area contains information about the instruction. the fields of the i/o trap dword are configured as follows: n bits 31C16 i/o port address n bits 15C4 reserved n bit 3 rep (repeat) string operation (1 = rep string, 0 = not a rep string) n bit 2 i/o string operation (1 = i/o string, 0 = not an i/o string) n bit 1 valid i/o instruction (1 = valid, 0 = invalid) n bit 0 input or output instruction (1 = inx, 0 = outx) table 36 shows the format of the i/o trap dword. table 36. i/o trap dword configuration 31 16 154 3 2 1 0 i/o port address reserved rep string operation i/o string operation valid i/o instruction input or output
chapter 10 system management mode (smm) 201 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information the i/o trap dword is related to the i/o trap restart slot (see i/o trap restart slot). if bit 1 of the i/o trap dword is set by the processor, it means that smi# was asserted during the execution of an i/o instruction. the smi handler tests bit 1 to see if there is a valid i/o instruction trapped. if the i/o instruction is valid, the smi handler is required to ensure the i/o trap restart slot is set properly. the i/o trap restart slot informs the cpu whether it should re-execute the i/o instruction after the rsm or execute the instruction following the trapped i/o instruction. note: if smi# is sampled asserted during an i/o bus cycle a minimum of three clock edges before brdy# is sampled asserted, the associated i/o instruction is guaranteed to be trapped by the smi handler. 10.8 i/o trap restart slot the i/o trap restart slot at offset ff00h in the smm state-save area specifies whether the trapped i/o instruction should be re-executed on return from smm. this slot in the state-save area is called the i/o instruction restart function. re-executing a trapped i/o instruction is useful, for example, if an i/o write occurs to a disk that is powered down. the system logic monitoring such an access can assert smi#. then the smm service routine would query the system logic, detect a failed i/o write, take action to power-up the i/o device, enable the i/o trap restart slot feature, and return from smm. the fields of the i/o trap restart slot are defined as follows: n bits 31C16 reserved n bits 15C0 i/o instruction restart on return from smm: 0000h = execute the next instruction after the trapped i/o instruction 00ffh = re-execute the trapped i/o instruction table 37 shows the format of the i/o trap restart slot. table 37. i/o trap restart slot 31C16 15C0 reserved i/o instruction restart on return from smm: n 0000h = execute the next instruction after the trapped i/o n 00ffh = re-execute the trapped i/o instruction
202 system management mode (smm) chapter 10 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information the processor initializes the i/o trap restart slot to 0000h upon entry into smm. if smm was entered due to a trapped i/o instruction, the processor indicates the validity of the i/o instruction by setting or clearing bit 1 of the i/o trap dword at offset ffa4h in the smm state-save area. the smm service routine should test bit 1 of the i/o trap dword to determine if a valid i/o instruction was being executed when entering smm and before writing the i/o trap restart slot. if the i/o instruction is valid, the smm service routine can safely rewrite the i/o trap restart slot with the value 00ffh, which causes the processor to re-execute the trapped i/o instruction when the rsm instruction is executed. if the i/o instruction is invalid, writing the i/o trap restart slot has undefined results. if a second smi# is asserted and a valid i/o instruction was trapped by the first smm handler, the cpu services the second smi# prior to re-executing the trapped i/o instruction. the second entry into smm never has bit 1 of the i/o trap dword set, and the second smm service routine must not rewrite the i/o trap restart slot. during a simultaneous smi# i/o instruction trap and debug breakpoint trap, the amd-k6 processor first responds to the smi# and postpones recognizing the debug exception until after returning from smm via the rsm instruction. if the debug registers dr3Cdr0 are used while in smm, they must be saved and restored by the smm handler. the processor automatically saves and restores dr7Cdr6. if the i/o trap restart slot in the smm state-save area contains the value 00ffh when the rsm instruction is executed, the debug trap does not occur until after the i/o instruction is re-executed. 10.9 exceptions, interrupts, and debug in smm during an smi# i/o trap, the exception/interrupt priority of the amd-k6 processor changes from its normal priority. the normal priority places the debug traps at a priority higher than the sampling of the flush# or smi# signals. however, during an smi# i/o trap, the sampling of the flush# or smi# signals takes precedence over debug traps. the processor recognizes the assertion of nmi within smm immediately after the completion of an iret instruction. once nmi is recognized within smm, nmi recognition remains enabled until smm is exited, at which point nmi masking is restored to the state it was in before entering smm.
chapter 11 test and debug 203 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 11 test and debug the amd-k6 processor implements various test and debug modes to enable the functional and manufacturing testing of systems and boards that use the processor. in addition, the debug features of the processor allow designers to debug the instruction execution of software components. this chapter describes the following test and debug features: n built-in self-test (bist) the bist, which is invoked after the falling transition of reset, runs internal tests that exercise most on-chip ram structures. n tri-state test mode a test mode that causes the processor to float its output and bidirectional pins. n boundary-scan test access port (tap) the joint test action group (jtag) test access function defined by the ieee standard test access port and boundary-scan architecture (ieee 1149.1-1990) specification. n level-one (l1) cache inhibit a feature that disables the processors internal l1 instruction and data caches. n debug support consists of all x86-compatible software debug features, including the debug extensions. 11.1 built-in self-test (bist) following the falling transition of reset, the processor unconditionally runs its bist. the internal resources tested during bist include the following: n l1 instruction and data caches n instruction and data translation lookaside buffers (tlbs) the contents of the eax general-purpose register after the completion of reset indicate if the bist was successful. if eax contains 0000_0000h, then bist was successful. if eax is non-zero, the bist failed. following the completion of the bist, the processor jumps to address ffff_fff0h to start instruction execution, regardless of the outcome of the bist. the bist takes approximately 295,000 processor clocks to complete.
204 test and debug chapter 11 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 11.2 tri-state test mode the tri-state test mode causes the processor to float its output and bidirectional pins, which is useful for board-level manufacturing testing. in this mode, the processor is electrically isolated from other components on a system board, allowing automated test equipment (ate) to test components that drive the same signals as those the processor floats. if the flush# signal is sampled low during the falling transition of reset, the processor enters the tri-state test mode. (see flush# (cache flush) on page 97 for the specific sampling requirements.) the signals floated in the tri-state test mode are as follows: the vcc2det and tdo signals are the only outputs not floated in the tri-state test mode. vcc2det must remain low to ensure the system continues to supply the specified processor core voltage to the v cc2 pins. tdo is never floated because the boundary-scan test access port must remain enabled at all times, including during the tri-state test mode. the tri-state test mode is exited when the processor samples reset asserted. n a[31:3] n d/c# n m/io# n ads# n d[63:0] n pcd n adsc# n dp[7:0] n pchk# n ap n ferr# n pwt n apchk# n hit# n scyc n be[7:0]# n hitm# n smiact# n breq n hlda n w/r# n cache# n lock#
chapter 11 test and debug 205 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 11.3 boundary-scan test access port (tap) the boundary-scan test access port (tap) is an ieee standard that defines synchronous scanning test methods for complex logic circuits, such as boards containing a processor. the amd-k6 processor supports the tap standard defined in the ieee standard test access port and boundary-scan architecture (ieee 1149.1-1990) specification. boundary scan testing uses a shift register consisting of the serial interconnection of boundary-scan cells that correspond to each i/o buffer of the processor. this non-inverting register chain, called a boundary scan register (bsr), can be used to capture the state of every processor pin and to drive every processor output and bidirectional pin to a known state. each bsr of every component on a board that implements the boundary-scan architecture can be serially interconnected to enable component interconnect testing. test access port the tap consists of the following: n test access port (tap) controller the tap controller is a synchronous, finite state machine that uses the tms and tdi input signals to control a sequence of test operations. see tap controller state machine on page 212 for a list of tap states and their definition. n instruction register (ir) the ir contains the instructions that select the test operation to be performed and the test data register (tdr) to be selected. see tap registers on page 206 for more details on the ir. n test data registers (tdr) the three tdrs are used to process the test data. each tdr is selected by an instruction in the instruction register (ir). see tap registers on page 206 for a list of these registers and their functions. tap signals the test signals associated with the tap controller are as follows: n tck the test clock for all tap operations. the rising edge of tck is used for sampling tap signals, and the falling edge of tck is used for asserting tap signals. the state of the tms signal sampled on the rising edge of tck causes
206 test and debug chapter 11 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information the state transitions of the tap controller to occur. tck can be stopped in the logic 0 or 1 state. n tdi the test data input represents the input to the most significant bit of all tap registers, including the ir and all test data registers. test data and instructions are serially shifted by one bit into their respective registers on the rising edge of tck. n tdo the test data output represents the output of the least significant bit of all tap registers, including the ir and all test data registers. test data and instructions are serially shifted by one bit out of their respective registers on the falling edge of tck. n tms the test mode select input specifies the test function and sequence of state changes for boundary-scan testing. if tms is sampled high for five or more consecutive clocks, the tap controller enters its reset state. n trst# the test reset signal is an asynchronous reset that unconditionally causes the tap controller to enter its reset state. refer to electrical data on page 233 and signal switching characteristics on page 241 to obtain the electrical specifications of the test signals. tap registers the amd-k6 processor provides an instruction register (ir) and three test data registers (tdr) to support the boundary-scan architecture. the ir and one of the tdrsthe boundary-scan register (bsr)consist of a shift register and an output register. the shift register is loaded in parallel in the capture states. (see tap controller state machine on page 212 for a description of the tap controller states.) in addition, the shift register is loaded and shifted serially in the shift states. the output register is loaded in parallel from its corresponding shift register in the update states. instruction register (ir). the ir is a 5-bit register, without parity, that determines which instruction to run and which test data register to select. when the tap controller enters the capture-ir state, the processor loads the following bits into the ir shift register: n 01b loaded into the two least significant bits, as specified by the ieee 1149.1 standard n 000b loaded into the three most significant bits
chapter 11 test and debug 207 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information loading 00001b into the ir shift register during the capture-ir state results in loading the sample/preload instruction. for each entry into the shift-ir state, the ir shift register is serially shifted by one bit toward the tdo pin. during the shift, the most significant bit of the ir shift register is loaded from the tdi pin. the ir output register is loaded from the ir shift register in the update-ir state, and the current instruction is defined by the ir output register. see tap instructions on page 211 for a list and definition of the instructions supported by the amd-k6. boundary scan register (bsr). the bsr is a test data register consisting of the interconnection of 152 boundary-scan cells. each output and bidirectional pin of the processor requires a two-bit cell, where one bit corresponds to the pin and the other bit is the output enable for the pin. when a 0 is shifted into the enable bit of a cell, the corresponding pin is floated, and when a 1 is shifted into the enable bit, the pin is driven valid. each input pin requires a one-bit cell that corresponds to the pin. the last cell of the bsr is reserved and does not correspond to any processor pin. the total number of bits that comprise the bsr is 281. table 38 on page 209 lists the order of these bits, where tdi is the input to bit 280, and tdo is driven from the output of bit 0. the entries listed as pin _e (where pin is an output or bidirectional signal) are the enable bits. if the bsr is the register selected by the current instruction and the tap controller is in the capture-dr state, the processor loads the bsr shift register as follows: n if the current instruction is sample/preload, then the current state of each input, output, and bidirectional pin is loaded. a bidirectional pin is treated as an output if its enable bit equals 1, and it is treated as an input if its enable bit equals 0. n if the current instruction is extest, then the current state of each input pin is loaded. a bidirectional pin is treated as an input, regardless of the state of its enable.
208 test and debug chapter 11 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information while in the shift-dr state, the bsr shift register is serially shifted toward the tdo pin. during the shift, bit 280 of the bsr is loaded from the tdi pin. the bsr output register is loaded with the contents of the bsr shift register in the update-dr state. if the current instruction is extest, the processors output pins, as well as those bidirectional pins that are enabled as outputs, are driven with their corresponding values from the bsr output register.
chapter 11 test and debug 209 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information table 38. boundary scan bit definitions bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable 280 d35_e 247 d21 214 d4_e 181 a3 148 a20 115 a16 279 d35 246 d18_e 213 d4 180 a31_e 147 a13_e 114 ferr_e 278 d29_e 245 d18 212 dp0_e 179 a31 146 a13 113 ferr# 277 d29 244 d19_e 211 dp0 178 a21_e 145 dp7_e 112 hit_e 276 d33_e 243 d19 210 hold 177 a21 144 dp7 111 hit# 275 d33 242 d16_e 209 boff# 176 a30_e 143 be6_e 110 be7_e 274 d27_e 241 d16 208 ahold 175 a30 142 be6# 109 be7# 273 d27 240 d17_e 207 stpclk# 174 a7_e 141 a12_e 108 na# 272 dp3_e 239 d17 206 init 173 a7 140 a12 107 adsc_e 271 dp3 238 d15_e 205 ignne# 172 a24_e 139 clk 106 adsc# 270 d25_e 237 d15 204 bf1 171 a24 138 be4_e 105 be5_e 269 d25 236 dp1_e 203 bf2 170 a18_e 137 be4# 104 be5# 268 d0_e 235 dp1 202 r eset 169 a18 136 a10_e 103 wb/w t# 267 d0 234 d13_e 201 bf0 168 a5_e 135 a10 102 pwt_e 266 d30_e 233 d13 200 flush# 167 a5 134 d63_e 101 pwt 265 d30 232 d6_e 199 intr 166 a22_e 133 d63 100 be3_e 264 dp2_e 231 d6 198 nmi 165 a22 132 be2_e 99 be3# 263 dp2 230 d14_e 197 smi# 164 eads# 131 be2# 98 breq_e 262 d2_e 229 d14 196 a25_e 163 a4_e 130 a15_e 97 breq 261 d2 228 d11_e 195 a25 162 a4 129 a15 96 pcd_e 260 d28_e 227 d11 194 a23_e 161 hitm_e 128 brdy# 95 pcd 259 d28 226 d1_e 193 a23 160 hitm# 127 be1_e 94 wr_e 258 d24_e 225 d1 192 a26_e 159 a9_e 126 be1# 93 w/r# 257 d24 224 d12_e 191 a26 158 a9 125 a14_e 92 smiact_e 256 d26_e 223 d12 190 a29_e 157 scyc_e 124 a14 91 smiact# 255 d26 222 d10_e 189 a29 156 scyc 123 brdyc# 90 ewbe# 254 d22_e 221 d10 188 a28_e 155 a8_e 122 be0_e 89 dc_e 253 d22 220 d7_e 187 a28 154 a8 121 be0# 88 d/c# 252 d23_e 219 d7 186 a27_e 153 a19_e 120 a17_e 87 apchk_e 251 d23 218 d8_e 185 a27 152 a19 119 a17 86 apchk# 250 d20_e 217 d8 184 a11_e 151 a6_e 118 ken# 85 c ache_e 249 d20 216 d9_e 183 a11 150 a6 117 a20m# 84 c ache# 248 d21_e 215 d9 182 a3_e 149 a20_e 116 a16_e 83 ads_e
210 test and debug chapter 11 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information device identification register (dir). the dir is a 32-bit test data register selected during the execution of the idcode instruction. the fields of the dir and their values are shown in table 39 and are defined as follows: n version code this 4-bit field is incremented by amd manufacturing for each major revision of silicon. n part number this 16-bit field identifies the specific processor model. n manufacturer this 11-bit field identifies the manufacturer of the component (amd). n lsb the least significant bit (lsb) of the dir is always set to 1, as specified by the ieee 1149.1 standard. 82 ads# 68 dp6_e 54 d53_e 40 d43_e 26 d38_e 12 d3_e 81 ap_e 67 dp6 53 d53 39 d43 25 d38 11 d3 80 ap 66 d54_e 52 d47_e 38 d62_e 24 d58_e 10 d39_e 79 inv 65 d54 51 d47 37 d62 23 d58 9 d39 78 hlda_e 64 d50_e 50 d59_e 36 d49_e 22 d42_e 8 d32_e 77 hlda 63 d50 49 d59 35 d49 21 d42 7 d32 76 pchk_e 62 d56_e 48 d51_e 34 dp4_e 20 d36_e 6 d5_e 75 pchk# 61 d56 47 d51 33 dp4 19 d36 5 d5 74 lock_e 60 d55_e 46 d45_e 32 d46_e 18 d60_e 4 d37_e 73 lock# 59 d55 45 d45 31 d46 17 d60 3 d37 72 mio_e 58 d48_e 44 d61_e 30 d41_e 16 d40_e 2 d31_e 71 m/io# 57 d48 43 d61 29 d41 15 d40 1 d31 70 d52_e 56 d57_e 42 dp5_e 28 d44_e 14 d34_e 0 reserved 69 d52 55 d57 41 dp5 27 d44 13 d34 table 38. boundary scan bit definitions (continued) bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable table 39. device identification register version code (bits 31C28) part number (bits 27C12) manufacturer (bits 11C1) lsb (bit 0) xh 0560h 00000000001b 1b
chapter 11 test and debug 211 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information bypass register (br). the br is a test data register consisting of a 1-bit shift register that provides the shortest path between tdi and tdo. when the processor is not involved in a test operation, the br can be selected by an instruction to allow the transfer of test data through the processor without having to serially scan the test data through the bsr. this functionality preserves the state of the bsr and significantly reduces test time. the br register is selected by the bypass and highz instructions as well as by any instructions not supported by the amd-k6. tap instructions the processor supports the three instructions required by the ieee 1149.1 standardextest, sample/preload, and bypassas well as two additional optional instructions idcode and highz. table 40 shows the complete set of tap instructions supported by the processor along with the 5-bit instruction register encoding and the register selected by each instruction. extest. when the extest instruction is executed, the processor loads the bsr shift register with the current state of the input and bidirectional pins in the capture-dr state and drives the output and bidirectional pins with the corresponding values from the bsr output register in the update-dr state. table 40. supported tap instructions instruction encoding register description extest 1 00000b bsr sample inputs and drive outputs sample / preload 00001b bsr sample inputs and outputs, then load the bsr idcode 00010b dir read dir highz 00011b br float outputs and bidirectional pins bypass 2 00100b C11110b br undefined instruction, execute the bypass instruction bypass 3 11111b br connect tdi to tdo to bypass the bsr notes: 1. following the execution of the extest instruction, the processor must be reset in order to return to normal, non-test operati on. 2. these instruction encodings are undefined on the amd-k6 processor and default to the bypass instruction. 3. because the tdi input contains an internal pullup, the bypass instruction is executed if the tdi input is not connected or op en during an instruction scan operation. the bypass instruction does not affect the normal operational state of the processor.
212 test and debug chapter 11 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information sample/preload. the sample/preload instruction performs two functions. these functions are as follows: n during the capture-dr state, the processor loads the bsr shift register with the current state of every input, output, and bidirectional pin. n during the update-dr state, the bsr output register is loaded from the bsr shift register in preparation for the next extest instruction. the sample/preload instruction does not affect the normal operational state of the processor. bypass. the bypass instruction selects the br register, which reduces the boundary-scan length through the processor from 281 to one (tdi to br to tdo). the bypass instruction does not affect the normal operational state of the processor. idcode. the idcode instruction selects the dir register, allowing the device identification code to be shifted out of the processor. this instruction is loaded into the ir when the tap controller is reset. the idcode instruction does not affect the normal operational state of the processor. highz. the highz instruction forces all output and bidirectional pins to be floated. during this instruction, the br is selected and the normal operational state of the processor is not affected. tap controller state machine the tap controller state diagram is shown in figure 73 on page 213. state transitions occur on the rising edge of tck. the logic 0 or 1 next to the states represents the value of the tms signal sampled by the processor on the rising edge of tck.
chapter 11 test and debug 213 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 73. tap state diagram test-logic-reset shift-dr pause-dr update-dr update-ir 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 run-test/idle exit2-ir exit1-ir pause-ir shift-ir select-dr-scan select-ir-scan capture-dr capture-ir exit1-dr exit2-dr ieee std 1149.1-1990, copyright ? 1990. ieee. all rights reserved
214 test and debug chapter 11 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information the states of the tap controller are described as follows: test-logic-reset. this state represents the initial reset state of the tap controller and is entered when the processor samples reset asserted, when trst# is asynchronously asserted, and when tms is sampled high for five or more consecutive clocks. in addition, this state can be entered from the select-ir-scan state. the ir is initialized with the idcode instruction, and the processors normal operation is not affected in this state. capture-dr. during the sample/preload instruction, the processor loads the bsr shift register with the current state of every input, output, and bidirectional pin. during the extest instruction, the processor loads the bsr shift register with the current state of every input and bidirectional pin. capture-ir. when the tap controller enters the capture-ir state, the processor loads 01b into the two least significant bits of the ir shift register and loads 000b into the three most significant bits of the ir shift register. shift-dr. while in the shift-dr state, the selected tdr shift register is serially shifted toward the tdo pin. during the shift, the most significant bit of the tdr is loaded from the tdi pin. shift-ir. while in the shift-ir state, the ir shift register is serially shifted toward the tdo pin. during the shift, the most significant bit of the ir is loaded from the tdi pin. update-dr. during the sample/preload instruction, the bsr output register is loaded with the contents of the bsr shift register. during the extest instruction, the output pins, as well as those bidirectional pins defined as outputs, are driven with their corresponding values from the bsr output register. update-ir. in this state, the ir output register is loaded from the ir shift register, and the current instruction is defined by the ir output register.
chapter 11 test and debug 215 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information the following states have no effect on the normal or test operation of the processor other than as shown in figure 73 on page 213: n run-test/idlethis state is an idle state between scan operations. n select-dr-scanthis is the initial state of the test data register state transitions. n select-ir-scanthis is the initial state of the instruction register state transitions. n exit1-drthis state is entered to terminate the shifting process and enter the update-dr state. n exit1-irthis state is entered to terminate the shifting process and enter the update-ir state. n pause-drthis state is entered to temporarily stop the shifting process of a test data register. n pause-irthis state is entered to temporarily stop the shifting process of the instruction register. n exit2-drthis state is entered in order to either terminate the shifting process and enter the update-dr state or to resume shifting following the exit from the pause-dr state. n exit2-irthis state is entered in order to either terminate the shifting process and enter the update-ir state or to resume shifting following the exit from the pause-ir state. 11.4 l1 cache inhibit purpose the amd-k6 processor provides a means for inhibiting the normal operation of its l1 instruction and data caches while still supporting an external level-2 (l2) cache. this capability allows system designers to disable the l1 cache during the testing and debug of an l2 cache. if the cache inhibit bit (bit 3) of test register 12 (tr12) is set to 0, the processors l1 cache is enabled and operates as described in cache organization on page 171. if the cache inhibit bit is set to 1, the l1 cache is disabled and no new cache lines are allocated. even though new allocations do not occur, valid l1 cache lines remain valid and are read by the processor when a requested address hits a cache line. in addition, the processor continues to support inquire cycles initiated by the
216 test and debug chapter 11 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information system logic, including the execution of writeback cycles when a modified cache line is hit. while the l1 is inhibited, the processor continues to drive the pcd output signal appropriately, which system logic can use to control external l2 caching. in order to completely disable the l1 cache so no valid lines exist in the cache, the cache inhibit bit must be set to 1 and the cache must be flushed in one of the following ways: n by asserting the flush# input signal n by executing the wbinvd instruction n by executing the invd instruction (modified cache lines are not written back to memory) 11.5 debug the amd-k6 processor implements the standard x86 debug functions, registers, and exceptions. in addition, the processor supports the i/o breakpoint debug extension. the debug feature assists programmers and system designers during software execution tracing by generating exceptions when one or more events occur during processor execution. the exception handler, or debugger, can be written to perform various tasks, such as displaying the conditions that caused the breakpoint to occur, displaying and modifying register or memory contents, or single-stepping through program execution. the following sections describe the debug registers and the various types of breakpoints and exceptions that the processor supports. debug registers figures 74 through 77 show the 32-bit debug registers supported by the processor.
chapter 11 test and debug 217 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 74. debug register dr7 symbol description bit gd general detect enabled 13 ge global exact breakpoint enabled 9 le local exact breakpoint enabled 8 g3 global exact breakpoint # 3 enabled 7 l3 local exact breakpoint # 3 enabled 6 g2 global exact breakpoint # 2 enabled 5 l2 local exact breakpoint # 2 enabled 4 g1 global exact breakpoint # 1 enabled 3 l1 local exact breakpoint # 1 enabled 2 g0 global exact breakpoint # 0 enabled 1 l0 local exact breakpoint # 0 enabled 0 9876543210 10 11 12 13 14 15 l 2 l 1 l 3 g 3 g e l e l 0 reserved g 0 g 1 l 2 g d 25 24 23 22 21 20 19 18 17 16 26 27 28 29 30 31 r/w 3 len 3 r/w 2 len 2 r/w 1 len 1 r/w 0 len 0 symbol description bits len 3 length of breakpoint #3 31C30 r/w 3 type of transaction(s) to trap 29C28 len 2 length of breakpoint #2 27C26 r/w 2 type of transaction(s) to trap 25C24 len 1 length of breakpoint #1 23C22 r/w 1 type of transaction(s) to trap 21C20 len 0 length of breakpoint #0 19C18 r/w 0 type of transaction(s) to trap 17C16
218 test and debug chapter 11 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 75. debug register dr6 figure 76. debug registers dr5 and dr4 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 b 1 b 2 b s b 0 reserved b t b d symbol description bit bt breakpoint task switch 15 bs breakpoint single step 14 bd breakpoint debug access detected 13 b3 breakpoint #3 condition detected 3 b2 breakpoint #2 condition detected 2 b1 breakpoint #1 condition detected 1 b0 breakpoint #0 condition detected 0 b 3 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr5 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr4
chapter 11 test and debug 219 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 77. debug registers dr3, dr2, dr1, and dr0 d r3Cdr0. the processor allows the setting of up to four breakpoints. dr3Cdr0 contain the linear addresses for breakpoint 3 through breakpoint 0, respectively, and are compared to the linear addresses of processor cycles to determine if a breakpoint occurs. debug register dr7 defines the specific type of cycle that must occur in order for the breakpoint to occur. dr5Cdr4. when debugging extensions are disabled (bit 3 of cr4 is set to 0), the dr5 and dr4 registers are mapped to dr7 and dr6, respectively, in order to be software compatible with previous generations of x86 processors. when debugging 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 3 32-bit linear address dr3 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 0 32-bit linear address dr0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 2 32-bit linear address dr2 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 1 32-bit linear address dr1
220 test and debug chapter 11 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information extensions are enabled (bit 3 of cr4 is set to 1), any attempt to load dr5 or dr4 results in an undefined opcode exception. likewise, any attempt to store dr5 or dr4 also results in an undefined opcode exception. dr6. if a breakpoint is enabled in dr7, and the breakpoint conditions as defined in dr7 occur, then the corresponding b-bit (b3Cb0) in dr6 is set to 1. in addition, any other breakpoints defined using these particular breakpoint conditions are reported by the processor by setting the appropriate b-bits in dr6, regardless of whether these breakpoints are enabled or disabled. however, if a breakpoint is not enabled, a debug exception does not occur for that breakpoint. if the processor decodes an instruction that writes or reads dr7 through dr0, the bd bit (bit 13) in dr6 is set to 1 (if enabled in dr7) and the processor generates a debug exception. this operation allows control to pass to the debugger prior to debug register access by software. if the trap flag (bit 8) of the eflags register is set to 1, the processor generates a debug exception after the successful execution of every instruction (single-step operation) and sets the bs bit (bit 14) in dr6 to indicate the source of the exception. when the processor switches to a new task and the debug trap bit (t-bit) in the corresponding task state segment (tss) is set to 1, the processor sets the bt bit (bit 15) in dr6 and generates a debug exception. dr7. when set to 1, l3Cl0 locally enable breakpoints 3 through 0, respectively. l3Cl0 are set to 0 whenever the processor executes a task switch. setting l3Cl0 to 0 disables the breakpoints and ensures that these particular debug exceptions are only generated for a specific task. when set to 1, g3Cg0 globally enable breakpoints 3 through 0, respectively. unlike l3Cl0, g3Cg0 are not set to 0 whenever the processor executes a task switch. not setting g3Cg0 to 0 allows breakpoints to remain enabled across all tasks. if a breakpoint is enabled globally but disabled locally, the global enable overrides the local enable.
chapter 11 test and debug 221 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information the le (bit 8) and ge (bit 9) bits in dr7 have no effect on the operation of the processor and are provided in order to be software compatible with previous generations of x86 processors. when set to 1, the gd bit in dr7 (bit 13) enables the debug exception associated with the bd bit (bit 13) in dr6. this bit is set to 0 when a debug exception is generated. len3Clen0 and rw3Crw0 are two-bit fields in dr7 that specify the length and type of each breakpoint as defined in table 41 . debug exceptions a debug exception is categorized as either a debug trap or a debug fault. a debug trap calls the debugger following the execution of the instruction that caused the trap. a debug fault calls the debugger prior to the execution of the instruction that caused the fault. all debug traps and faults generate either an interrupt 01h or an interrupt 03h exception. table 41. dr7 len and rw definitions len bits 1 rw bits breakpoint 00b 00b 2 instruction execution 00b 01b one-byte data write 01b two-byte data write 11b four-byte data write 00b 10b 3 one-byte i/o read or write 01b two-byte i/o read or write 11b four-byte i/o read or write 00b 11b one-byte data read or write 01b two-byte data read or write 11b four-byte data read or write notes: 1. len bits equal to 10b is undefined. 2. when rw equals 00b, len must be equal to 00b. 3. when rw equals 10b, debugging extensions (de) must be enabled (bit 3 of cr4 must be set to 1). if de is set to 0, then rw equal to 10b is undefined.
222 test and debug chapter 11 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information interrupt 01h. the following events are considered debug traps that cause the processor to generate an interrupt 01h exception: n enabled breakpoints for data and i/o cycles n single step trap n task switch trap the following events are considered debug faults that cause the processor to generate an interrupt 01h exception: n enabled breakpoints for instruction execution n bd bit in dr6 set to 1 interrupt 03h. the int 3 instruction is defined in the x86 architecture as a breakpoint instruction. this instruction causes the processor to generate an interrupt 03h exception. this exception is a debug trap because the debugger is called following the execution of the int 3 instruction. the int 3 instruction is a one-byte instruction (opcode cch) typically used to insert a breakpoint in software by writing cch to the address of the first byte of the instruction to be trapped (the target instruction). following the trap, if the target instruction is to be executed, the debugger must replace the int 3 instruction with the first byte of the target instruction.
chapter 12 clock control 223 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 12 clock control the amd-k6 processor supports five modes of clock control. the processor can transition between these modes to maximize performance, to minimize power dissipation, or to provide a balance between performance and power. (see power dissipation on page 235 for the maximum power dissipation of the amd-k6 processor within the normal and reduced-power states.) the five clock-control states supported are as follows: n normal state : the processor is running in real mode, virtual-8086 mode, protected mode, or system management mode (smm). in this state, all clocks are runningincluding the external bus clock clk and the internal processor clockand the full features and functions of the processor are available. n halt state : this low-power state is entered following the successful execution of the hlt instruction. during this state, the internal processor clock is stopped. n stop grant state : this low-power state is entered following the recognition of the assertion of the stpclk# signal. during this state, the internal processor clock is stopped. n stop grant inquire state : this state is entered from the halt state and the stop grant state as the result of a system-initiated inquire cycle. n stop clock state : this low-power state is entered from the stop grant state when the clk signal is stopped. the following sections describe each of the four low-power states. figure 78 on page 228 illustrates the clock control state transitions.
224 clock control chapter 12 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 12.1 halt state enter halt state during the execution of the hlt instruction, the amd-k6 processor executes a halt special cycle. after brdy# is sampled asserted during this cycle, and then ewbe# is also sampled asserted, the processor enters the halt state in which the processor disables most of its internal clock distribution. in order to support the following operations, the internal phase-lock loop (pll) still runs, and some internal resources are still clocked in the halt state: n inquire cycles: the processor continues to sample ahold, boff#, and hold in order to support inquire cycles that are initiated by the system logic. the processor transitions to the stop grant inquire state during the inquire cycle. after returning to the halt state following the inquire cycle, the processor does not execute another halt special cycle. n flush cycles: the processor continues to sample flush#. if flush# is sampled asserted, the processor performs the flush operation in the same manner as it is performed in the normal state. upon completing the flush operation, the processor executes the halt special cycle which indicates the processor is in the halt state. n time stamp counter (tsc): the tsc continues to count in the halt state. n signal sampling: the processor continues to sample init, intr, nmi, reset, and smi#. after entering the halt state, all signals driven by the processor retain their state as they existed following the completion of the halt special cycle. exit halt state the amd-k6 processor remains in the halt state until it samples init, intr (if interrupts are enabled), nmi, reset, or smi# asserted. if any of these signals is sampled asserted, the processor returns to the normal state and performs the corresponding operation. all of the normal requirements for recognition of these input signals apply within the halt state.
chapter 12 clock control 225 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 12.2 stop grant state enter stop grant state after recognizing the assertion of stpclk#, the amd-k6 processor flushes its instruction pipelines, completes all pending and in-progress bus cycles, and acknowledges the stpclk# assertion by executing a stop grant special bus cycle. after brdy# is sampled asserted during this cycle, and then ewbe# is also sampled asserted, the processor enters the stop grant state. the stop grant state is like the halt state in that the processor disables most of its internal clock distribution in the stop grant state. in order to support the following operations, the internal pll still runs, and some internal resources are still clocked in the stop grant state: n inquire cycles: the processor transitions to the stop grant inquire state during an inquire cycle. after returning to the stop grant state following the inquire cycle, the processor does not execute another stop grant special cycle. n time stamp counter (tsc): the tsc continues to count in the stop grant state. n signal sampling: the processor continues to sample init, intr, nmi, reset, and smi#. flush# is not recognized in the stop grant state (unlike while in the halt state). upon entering the stop grant state, all signals driven by the processor retain their state as they existed following the completion of the stop grant special cycle. exit stop grant state the amd-k6 processor remains in the stop grant state until it samples stpclk# negated or reset asserted. if stpclk# is sampled negated, the processor returns to the normal state in less than 10 bus clock (clk) periods. after the transition to the normal state, the processor resumes execution at the instruction boundary on which stpclk# was initially recognized. if stpclk# is recognized as negated in the stop grant state and subsequently sampled asserted prior to returning to the normal state, the amd-k6 processor guarantees that a minimum of one instruction is executed prior to re-entering the stop grant state.
226 clock control chapter 12 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information if init, intr (if interrupts are enabled), flush#, nmi, or smi# are sampled asserted in the stop grant state, the processor latches the edge-sensitive signals (init, flush#, nmi, and smi#), but otherwise does not exit the stop grant state to service the interrupt. when the processor returns to the normal state due to sampling stpclk# negated, any pending interrupts are recognized after returning to the normal state. to ensure their recognition, all of the normal requirements for these input signals apply within the stop grant state. if reset is sampled asserted in the stop grant state, the processor immediately returns to the normal state and the reset process begins. 12.3 stop grant inquire state enter stop grant inquire state the stop grant inquire state is entered from the stop grant state or the halt state when eads# is sampled asserted during an inquire cycle initiated by the system logic. the amd-k6 processor responds to an inquire cycle in the same manner as in the normal state by driving hit# and hitm#. if the inquire cycle hits a modified data cache line, the processor performs a writeback cycle. exit stop grant inquire state following the completion of any writeback, the processor returns to the state from which it entered the stop grant inquire state. 12.4 stop clock state enter stop clock state if the clk signal is stopped while the amd-k6 processor is in the stop grant state, the processor enters the stop clock state. because all internal clocks and the pll are not running in the stop clock state, the stop clock state represents the minimum-power state of all clock control states. the clk signal must be held low while it is stopped. the stop clock state cannot be entered from the halt state. intr is the only input signal that is allowed to change states while the processor is in the stop clock state. however, intr is not sampled until the processor returns to the stop grant state.
chapter 12 clock control 227 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information all other input signals must remain unchanged in the stop clock state. exit stop clock state the amd-k6 processor returns to the stop grant state from the stop clock state after the clk signal is started and the internal pll has stabilized. pll stabilization is achieved after the clk signal has been running within its specification for a minimum of 1.0 ms. the frequency of clk when exiting the stop clock state can be different than the frequency of clk when entering the stop clock state. the state of the bf[2:0] signals when exiting the stop clock state is ignored because the bf[2:0] signals are only sampled during the falling transition of reset.
228 clock control chapter 12 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 78. clock control state transitions eads# asserted eads# asserted hlt instruction stop grant state normal mode - real - virtual-8086 - protected - smm halt state stop clock state reset, smi#, init, or intr asserted stop grant inquire state stpclk# asserted stpclk# negated, or reset asserted clk started clk stopped writeback completed writeback completed
chapter 13 power and grounding 229 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 13 power and grounding 13.1 power connections the amd-k6 processor is a dual voltage device. two separate supply voltages are required: v cc2 and v cc3 . v cc2 provides the core voltage for the processor and v cc3 provides the i/o voltage. see electrical data on page 233 for the value and range of v cc2 and v cc3 . there are 28 v cc2 , 32 v cc3 , and 68 v ss pins on the amd-k6 processor. (see pin designations on page 269 for all power and ground pin designations.) the large number of power and ground pins are provided to ensure that the processor and package maintain a clean and stable power distribution network. for proper operation and functionality, all v cc2 , v cc3 , and v ss pins must be connected to the appropriate planes in the circuit board. the power planes have been arranged in a pattern to simplify routing and minimize crosstalk on the circuit board. the isolation region between two voltage planes must be at least 0.254mm if they are in the same layer of the circuit board. (see figure 79 on page 230.) in order to maintain a low-impedance current sink and reference, the ground plane must never be split. although the amd-k6 has two separate supply voltages, there are no special power sequencing requirements. the best procedure is to minimize the time between which v cc2 and v cc3 are either both on or both off.
230 power and grounding chapter 13 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 79. suggested component placement 13.2 decoupling recommendations in addition to the isolation region mentioned in power connections on page 229, adequate decoupling capacitance is required between the two system power planes and the ground plane to minimize ringing and to provide a low-impedance path for return currents. suggested decoupling capacitor placement is shown in figure 79. surface mounted capacitors should be used under the processors zif socket to minimize resistance and inductance in the lead lengths while maintaining minimal height. for information and recommendations about the specific value, quantity, and location of the capacitors, see the amd-k6 ? processor power supply design application note , order# 21103. 0.254mm (min.) for isolation region v cc2 (core) plane v cc3 (i/o) plane c1 cc5 cc3 c2 + + + + c5 c6 c7 c11 c12 c13 c17 c18 c19 c20 c21 c22 c23 c24 c25 c26 c27 c28 c29 c30 c31 cc4 + cc6 cc10 cc1 cc2 cc9 cc8 cc7 c8 c9 c10 c14 c15 c16
chapter 13 power and grounding 231 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 13.3 pin connection requirements for proper operation, the following requirements for signal pin connections must be met: n do not drive address and data signals into large capacitive loads at high frequencies. if necessary, use buffer chips to drive large capacitive loads. n leave all nc (no-connect) pins unconnected. n unused inputs should always be connected to an appropriate signal level. ? active low inputs that are not being used should be connected to v cc3 through a 20k- w pullup resistor. ? active high inputs that are not being used should be connected to gnd through a pulldown resistor. n reserved signals can be treated in one of the following ways: ? as no-connect (nc) pins, in which case these pins are left unconnected ? as pins connected to the system logic as defined by the industry-standard pentium interface (socket 7) ? any combination of nc and socket 7 pins n keep trace lengths to a minimum.
232 power and grounding chapter 13 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 14 electrical data 233 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 14 electrical data 14.1 operating ranges the functional operation of the amd-k6 processor is guaranteed if the voltage and temperature parameters are within the limits defined in table 42. 14.2 absolute ratings while functional operation is not guaranteed beyond the operating ranges listed in table 42, no long-term reliability or functional damage is caused as long as the amd-k6 processor is not subjected to conditions exceeding the absolute ratings listed in table 43. table 42. operating ranges parameter minimum typical maximum comments v cc2 2.755 v 2.9 v 3.045 v note 1, 2 3.1 v 3.2 v 3.3 v note 1, 3 v cc3 3.135 v 3.3 v 3.6 v note 1 t case 0 c70 c notes: 1. v cc2 and v cc3 are referenced from v ss . 2. v cc2 specification for 2.9 v components. 3. v cc2 specification for 3.2 v components. table 43. absolute ratings parameter minimum maximum comments v cc2 C0.5 v 3.5 v v cc3 C0.5 v 4.0 v v pin C0.5 v v cc3 +0.5 v and note 4.0 v t case (under bias) C65 c +110 c t storage C65 c +150 c note: v pin (the voltage on any i/o pin) must not be greater than 0.5 v above the voltage being applied to v cc3 . in addition, the v pin voltage must never exceed 4.0 v.
234 electrical data chapter 14 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 14.3 dc characteristics the dc characteristics of the amd-k6 processor are shown in table 44. table 44. dc characteristics symbol parameter description preliminary data comments min max v il input low voltage C 0.3 v +0.8 v v ih input high voltage 2.0 v v cc3 +0.3 v note 1 v ol output low voltage 0.4 v i ol = 4.0-ma load v oh output high voltage 2.4 v i oh = 3.0-ma load i cc2 2.9 v power supply current 6.25 a 166 mhz, note 2 7.50 a 200 mhz, note 2 i cc2 3.2 v power supply current 9.50 a 233 mhz, note 3 i cc3 3.3 v power supply current 0.48 a 166 mhz, note 4 0.50 a 200 mhz, note 4 0.52 a 233 mhz, note 4 i li input leakage current 15 m anote 5 i lo output leakage current 15 m anote 5 i il input leakage current bias with pullup C400 m anote 6 i ih input leakage current bias with pulldown 200 m anote 7 c in input capacitance 15 pf c out output capacitance 20 pf c out i/o capacitance 25 pf c clk clk capacitance 15 pf c tin test input capacitance (tdi, tms, trst#) 15 pf c tout test output capacitance (tdo) 20 pf c tck tck capacitance 15 pf notes: 1. v cc3 refers to the voltage being applied to v cc3 during functional operation. 2. v cc2 = 3.045 v the maximum power supply current must be taken into account when designing a power supply. 3. v cc2 = 3.3 v the maximum power supply current must be taken into account when designing a power supply. 4. v cc3 = 3.6 v the maximum power supply current must be taken into account when designing a power supply. 5. refers to inputs and i/o without an internal pullup resistor and 0 v in v cc3. 6. refers to inputs with an internal pullup and v il = 0.4v. 7. refers to inputs with an internal pulldown and v ih = 2.4v.
chapter 14 electrical data 235 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 14.4 power dissipation table 45 contains the typical and maximum power dissipation of the amd-k6 processor during normal and reduced power states. table 45. typical and maximum power dissipation clock control state 2.9 v component 3.2 v component comments 166 mhz 200 mhz 233 mhz normal (maximum thermal power) 17.2 w 20.0 w 28.3 w note 1, 2 normal (typical thermal power) 10.3 w 12.0 w 17.0 w note 3 stop grant / halt (maximum) 1.45 w 1.53 w 1.75 w note 4 stop clock (maximum) 1.0 w 1.0 w 1.0 w note 5 notes: 1. the maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal dissipation for the amd-k6 processor. 2. maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with v cc2 = 2.9 v (for the 2.9 v component) or v cc2 = 3.2 v (for the 3.2 v component), and v cc3 = 3.3 v. 3. typical power is determined for the typical instruction sequences or functions associated with normal system operation with v cc2 = 2.9 v (for the 2.9 v component) or v cc2 = 3.2 v (for the 3.2 v component), and v cc3 = 3.3 v. 4. the clk signal and the internal pll are still running but most internal clocking has stopped. 5. the clk signal, the internal pll, and all internal clocking has stopped.
236 electrical data chapter 14 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 15 i/o buffer characteristics 237 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 15 i/o buffer characteristics all of the amd-k6 processor inputs, outputs, and bidirectional buffers are implemented using a 3.3v buffer design. in addition, a subset of the processor i/o buffers include a second, higher drive strength option. these buffers can be configured to provide the higher drive strength for applications that place a heavier load on these i/o signals. amd has developed two i/o buffer models that represent the characteristics of each of the two possible drive strength configurations supported by the amd-k6. these two models are called the standard i/o model and the strong i/o model. amd developed the two models to allow system designers to perform analog simulations of amd-k6 signals that interface with the system logic. analog simulations are used to determine a signals time of flight from source to destination and to ensure that the systems signal quality requirements are met. signal quality measurements include overshoot, undershoot, slope reversal, and ringing. 15.1 selectable drive strength the amd-k6 processor samples the brdyc# input during the falling transition of reset to configure the drive strength of a[20:3], ads#, hitm# and w/r#. if brdyc# is 0 during the fall of reset, these particular outputs are configured using the higher drive strength. if brdyc# is 1 during the fall of reset, the standard drive strength is selected for all i/o buffers. table 46 shows the relationship between brdyc# and the two available drive strengths k6std and k6stg. table 46. a[20:3], ads#, hitm#, and w/r# strength selection drive strength brdyc# i/o buffer name strength 1 (standard) 1 k6std strength 2 (strong) 0 k6stg
238 i/o buffer characteristics chapter 15 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 15.2 i/o buffer model amd provides models of the amd-k6 processor i/o buffers for system designers to use in board-level simulations. these i/o buffer models conform to the i/o buffer information specification (ibis), version 2.1 . the standard i/o model uses k6std, the standard i/o buffer representation, for all i/o buffers. the strong i/o model uses k6stg, the stronger i/o buffer representation for a[20:3], ads#, hitm#, and w/r#, and uses k6std for the remainder of the i/o buffers. both i/o models contain voltage versus current (v/i) and voltage versus time (v/t) data tables for accurate modeling of i/o buffer behavior. the following list characterizes the properties of each i/o buffer model: n all data tables contain minimum, typical, and maximum values to allow for worst-case, typical, and best-case simulations, respectively. n the pullup, pulldown, power clamp, and ground clamp device v/i tables contain enough data points to accurately represent the nonlinear nature of the v/i curves. in addition, the voltage ranges provided in these tables extend beyond the normal operating range of the amd-k6 processor for those simulators that yield more accurate results based on this wider range. figure 80 and figure 81 on page 239 illustrate the min/typ/max pulldown and pullup v/i curves for k6std between 0v and 3.3v. n the rising and falling ramp rates are specified. n the min/typ/max v cc3 operating range is specified as 3.135v, 3.3v, and 3.6v, respectively. n v il = 0.8v, v ih = 2.0v, and v meas = 1.5v n the r/l/c of the package is modeled. n the capacitance of the silicon die is modeled. n the model assumes the test load is 0 capacitance, resistance, inductance, and voltage.
chapter 15 i/o buffer characteristics 239 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 80. k6std pulldown v/i curves figure 81. k6std pullup v/i curves 15.3 i/o model application note for the amd-k6 processor i/o buffer ibis models and their application, refer to the amd-k6 ? processor i/o model (ibis) application note , order# 21084. 15.4 i/o buffer ac and dc characteristics see signal switching characteristics on page 241 for the amd-k6 processor ac timing specifications. see electrical data on page 233 for the amd-k6 processor dc specifications. 0 10 20 30 40 50 60 70 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 v output (v) i ol (ma) -70 -60 -50 -40 -30 -20 -10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 v output (v) i oh (ma)
240 i/o buffer characteristics chapter 15 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 16 signal switching characteristics 241 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 16 signal switching characteristics the amd-k6 processor signal switching characteristics are presented in table 47 through table 55. valid delay, float, setup, and hold timing specifications are listed. these specifications are provided for the system designer to determine if the timings necessary for the processor to interface with the system logic are met. table 47 and table 48 contain the switching characteristics of the clk input. table 49 through table 52 contain the timings for the normal operation signals. table 53 contains the timings for reset and the configuration signals. table 54 and table 55 contain the timings for the test operation signals. all signal timings provided are: n measured between clk, tck, or reset at 1.5 v and the corresponding signal at 1.5 v this applies to input and out- put signals that are switching from low to high, or from high to low n based on input signals applied at a slew rate of 1 v/ns between 0 v and 3 v (rising) and 3 v to 0 v (falling) n valid within the operating ranges given in operating ranges on page 233 n based on a load capacitance (c l ) of 0 pf 16.1 clk switching characteristics table 47 and table 48 contain the switching characteristics of the clk input to the amd-k6 processor for 66-mhz and 60-mhz bus operation, respectively, as measured at the voltage levels indicated by figure 82. the clk period stability specifies the variance (jitter) allowed between successive periods of the clk input measured at 1.5 v. this parameter must be considered as one of the elements of clock skew between the amd-k6 and the system logic.
242 signal switching characteristics chapter 16 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 16.2 clock switching characteristics for 66-mhz bus operation 16.3 clock switching characteristics for 60-mhz bus operation table 47. clk switching characteristics for 66-mhz bus operation symbol parameter description preliminary data figure comments min max frequency 33.3 mhz 66.6 mhz in normal mode t 1 clk period 15.0 ns 30.0 ns 82 in normal mode t 2 clk high time 4.0 ns 82 t 3 clk low time 4.0 ns 82 t 4 clk fall time 0.15 ns 1.5 ns 82 t 5 clk rise time 0.15 ns 1.5 ns 82 clk period stability 250 ps note note: jitter frequency power spectrum peaking must occur at frequencies greater than (frequency of clk)/3 or less than 500 khz. table 48. clk switching characteristics for 60-mhz bus operation symbol parameter description preliminary data figure comments min max frequency 30 mhz 60 mhz in normal mode t 1 clk period 16.67 ns 33.33 ns 82 in normal mode t 2 clk high time 4.0 ns 82 t 3 clk low time 4.0 ns 82 t 4 clk fall time 0.15 ns 1.5 ns 82 t 5 clk rise time 0.15 ns 1.5 ns 82 clk period stability 250 ps note note: jitter frequency power spectrum peaking must occur at frequencies greater than (frequency of clk)/3 or less than 500 khz.
chapter 16 signal switching characteristics 243 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 82. clk waveform 16.4 valid delay, float, setup, and hold timings valid delay and float timings are given for output signals during functional operation and are given relative to the rising edge of clk. during boundary-scan testing, valid delay and float timings for output signals are with respect to the falling edge of tck. the maximum valid delay timings are provided to allow a system designer to determine if setup times to the system logic can be met. likewise, the minimum valid delay timings are used to analyze hold times to the system logic. the setup and hold time requirements for the amd-k6 processor input signals must be met by the system logic to assure the proper operation of the amd-k6. the setup and hold timings during functional and boundary-scan test mode are given relative to the rising edge of clk and tck, respectively. t 5 2.0 v 1.5 v 0.8 v t 2 t 3 t 4 t 1
244 signal switching characteristics chapter 16 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 16.5 output delay timings for 66-mhz bus operation table 49. output delay timings for 66-mhz bus operation symbol parameter description preliminary data figure comments min max t 6 a[31:3] valid delay 1.1 ns 6.3 ns 84 t 7 a[31:3] float delay 10.0 ns 85 t 8 ads# valid delay 1.0 ns 6.0 ns 84 t 9 ads# float delay 10.0 ns 85 t 10 adsc# valid delay 1.0 ns 7.0 ns 84 t 11 adsc# float delay 10.0 ns 85 t 12 ap valid delay 1.0 ns 8.5 ns 84 t 13 ap float delay 10.0 ns 85 t 14 apchk# valid delay 1.0 ns 8.3 ns 84 t 15 be[7:0]# valid delay 1.0 ns 7.0 ns 84 t 16 be[7:0]# float delay 10.0 ns 85 t 17 breq valid delay 1.0 ns 8.0 ns 84 t 18 cache# valid delay 1.0 ns 7.0 ns 84 t 19 cache# float delay 10.0 ns 85 t 20 d/c# valid delay 1.0 ns 7.0 ns 84 t 21 d/c# float delay 10.0 ns 85 t 22 d[63:0] write data valid delay 1.3 ns 7.5 ns 84 t 23 d[63:0] write data float delay 10.0 ns 85 t 24 dp[7:0] write data valid delay 1.3 ns 7.5 ns 84 t 25 dp[7:0] write data float delay 10.0 ns 85 t 26 ferr# valid delay 1.0 ns 8.3 ns 84 t 27 hit# valid delay 1.0 ns 6.8 ns 84 t 28 hitm# valid delay 1.1 ns 6.0 ns 84 t 29 hlda valid delay 1.0 ns 6.8 ns 84 t 30 lock# valid delay 1.1 ns 7.0 ns 84 t 31 lock# float delay 10.0 ns 85 t 32 m/io# valid delay 1.0 ns 5.9 ns 84 t 33 m/io# float delay 10.0 ns 85
chapter 16 signal switching characteristics 245 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information t 34 pcd valid delay 1.0 ns 7.0 ns 84 t 35 pcd float delay 10.0 ns 85 t 36 pchk# valid delay 1.0 ns 7.0 ns 84 t 37 pwt valid delay 1.0 ns 7.0 ns 84 t 38 pwt float delay 10.0 ns 85 t 39 scyc valid delay 1.0 ns 7.0 ns 84 t 40 scyc float delay 10.0 ns 85 t 41 smiact# valid delay 1.0 ns 7.3 ns 84 t 42 w/r# valid delay 1.0 ns 7.0 ns 84 t 43 w/r# float delay 10.0 ns 85 table 49. output delay timings for 66-mhz bus operation (continued) symbol parameter description preliminary data figure comments min max
246 signal switching characteristics chapter 16 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 16.6 input setup and hold timings for 66-mhz bus operation table 50. input setup and hold timings for 66-mhz bus operation symbol parameter description preliminary data figure comments min max t 44 a[31:5] setup time 6.0 ns 86 t 45 a[31:5] hold time 1.0 ns 86 t 46 a20m# setup time 5.0 ns 86 note 1 t 47 a20m# hold time 1.0 ns 86 note 1 t 48 ahold setup time 5.5 ns 86 t 49 ahold hold time 1.0 ns 86 t 50 ap setup time 5.0 ns 86 t 51 ap hold time 1.0 ns 86 t 52 boff# setup time 5.5 ns 86 t 53 boff# hold time 1.0 ns 86 t 54 brdy# setup time 5.0 ns 86 t 55 brdy# hold time 1.0 ns 86 t 56 brdyc# setup time 5.0 ns 86 t 57 brdyc# hold time 1.0 ns 86 t 58 d[63:0] read data setup time 2.8 ns 86 t 59 d[63:0] read data hold time 1.5 ns 86 t 60 dp[7:0] read data setup time 2.8 ns 86 t 61 dp[7:0] read data hold time 1.5 ns 86 t 62 eads# setup time 5.0 ns 86 t 63 eads# hold time 1.0 ns 86 t 64 ewbe# setup time 5.0 ns 86 t 65 ewbe# hold time 1.0 ns 86 t 66 flush# setup time 5.0 ns 86 note 2 t 67 flush# hold time 1.0 ns 86 note 2 notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks.
chapter 16 signal switching characteristics 247 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information t 68 hold setup time 5.0 ns 86 t 69 hold hold time 1.5 ns 86 t 70 ignne# setup time 5.0 ns 86 note 1 t 71 ignne# hold time 1.0 ns 86 note 1 t 72 init setup time 5.0 ns 86 note 2 t 73 init hold time 1.0 ns 86 note 2 t 74 intr setup time 5.0 ns 86 note 1 t 75 intr hold time 1.0 ns 86 note 1 t 76 inv setup time 5.0 ns 86 t 77 inv hold time 1.0 ns 86 t 78 ken# setup time 5.0 ns 86 t 79 ken# hold time 1.0 ns 86 t 80 na# setup time 4.5 ns 86 t 81 na# hold time 1.0 ns 86 t 82 nmi setup time 5.0 ns 86 note 2 t 83 nmi hold time 1.0 ns 86 note 2 t 84 smi# setup time 5.0 ns 86 note 2 t 85 smi# hold time 1.0 ns 86 note 2 t 86 stpclk# setup time 5.0 ns 86 note 1 t 87 stpclk# hold time 1.0 ns 86 note 1 t 88 wb/wt# setup time 4.5 ns 86 t 89 wb/wt# hold time 1.0 ns 86 table 50. input setup and hold timings for 66-mhz bus operation (continued) symbol parameter description preliminary data figure comments min max notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks.
248 signal switching characteristics chapter 16 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 16.7 output delay timings for 60-mhz bus operation table 51. output delay timings for 60-mhz bus operation symbol parameter description preliminary data figure comments min max t 6 a[31:3] valid delay 1.1 ns 6.3 ns 84 t 7 a[31:3] float delay 10.0 ns 85 t 8 ads# valid delay 1.0 ns 7.0 ns 84 t 9 ads# float delay 10.0 ns 85 t 10 adsc# valid delay 1.0 ns 7.0 ns 84 t 11 adsc# float delay 10.0 ns 85 t 12 ap valid delay 1.0 ns 8.5 ns 84 t 13 ap float delay 10.0 ns 85 t 14 apchk# valid delay 1.0 ns 8.3 ns 84 t 15 be[7:0]# valid delay 1.0 ns 7.0 ns 84 t 16 be[7:0]# float delay 10.0 ns 85 t 17 breq valid delay 1.0 ns 8.0 ns 84 t 18 cache# valid delay 1.0 ns 7.0 ns 84 t 19 cache# float delay 10.0 ns 85 t 20 d/c# valid delay 1.0 ns 7.0 ns 84 t 21 d/c# float delay 10.0 ns 85 t 22 d[63:0] write data valid delay 1.3 ns 7.5 ns 84 t 23 d[63:0] write data float delay 10.0 ns 85 t 24 dp[7:0] write data valid delay 1.3 ns 7.5 ns 84 t 25 dp[7:0] write data float delay 10.0 ns 85 t 26 ferr# valid delay 1.0 ns 8.3 ns 84 t 27 hit# valid delay 1.0 ns 8.0 ns 84 t 28 hitm# valid delay 1.1 ns 6.0 ns 84 t 29 hlda valid delay 1.0 ns 8.0 ns 84 t 30 lock# valid delay 1.1 ns 7.0 ns 84 t 31 lock# float delay 10.0 ns 85 t 32 m/io# valid delay 1.0 ns 7.0 ns 84 t 33 m/io# float delay 10.0 ns 85
chapter 16 signal switching characteristics 249 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information t 34 pcd valid delay 1.0 ns 7.0 ns 84 t 35 pcd float delay 10.0 ns 85 t 36 pchk# valid delay 1.0 ns 7.0 ns 84 t 37 pwt valid delay 1.0 ns 7.0 ns 84 t 38 pwt float delay 10.0 ns 85 t 39 scyc valid delay 1.0 ns 7.0 ns 84 t 40 scyc float delay 10.0 ns 85 t 41 smiact# valid delay 1.0 ns 7.6 ns 84 t 42 w/r# valid delay 1.0 ns 7.0 ns 84 t 43 w/r# float delay 10.0 ns 85 table 51. output delay timings for 60-mhz bus operation (continued) symbol parameter description preliminary data figure comments min max
250 signal switching characteristics chapter 16 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 16.8 input setup and hold timings for 60-mhz bus operation table 52. input setup and hold timings for 60-mhz bus operation symbol parameter description preliminary data figure comments min max t 44 a[31:5] setup time 6.0 ns 86 t 45 a[31:5] hold time 1.0 ns 86 t 46 a20m# setup time 5.0 ns 86 note 1 t 47 a20m# hold time 1.0 ns 86 note 1 t 48 ahold setup time 5.5 ns 86 t 49 ahold hold time 1.0 ns 86 t 50 ap setup time 5.0 ns 86 t 51 ap hold time 1.0 ns 86 t 52 boff# setup time 5.5 ns 86 t 53 boff# hold time 1.0 ns 86 t 54 brdy# setup time 5.0 ns 86 t 55 brdy# hold time 1.0 ns 86 t 56 brdyc# setup time 5.0 ns 86 t 57 brdyc# hold time 1.0 ns 86 t 58 d[63:0] read data setup time 3.0 ns 86 t 59 d[63:0] read data hold time 1.5 ns 86 t 60 dp[7:0] read data setup time 3.0 ns 86 t 61 dp[7:0] read data hold time 1.5 ns 86 t 62 eads# setup time 5.5 ns 86 t 63 eads# hold time 1.0 ns 86 t 64 ewbe# setup time 5.0 ns 86 t 65 ewbe# hold time 1.0 ns 86 t 66 flush# setup time 5.0 ns 86 note 2 t 67 flush# hold time 1.0 ns 86 note 2 notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks.
chapter 16 signal switching characteristics 251 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information t 68 hold setup time 5.0 ns 86 t 69 hold hold time 1.5 ns 86 t 70 ignne# setup time 5.0 ns 86 note 1 t 71 ignne# hold time 1.0 ns 86 note 1 t 72 init setup time 5.0 ns 86 note 2 t 73 init hold time 1.0 ns 86 note 2 t 74 intr setup time 5.0 ns 86 note 1 t 75 intr hold time 1.0 ns 86 note 1 t 76 inv setup time 5.0 ns 86 t 77 inv hold time 1.0 ns 86 t 78 ken# setup time 5.0 ns 86 t 79 ken# hold time 1.0 ns 86 t 80 na# setup time 4.5 ns 86 t 81 na# hold time 1.0 ns 86 t 82 nmi setup time 5.0 ns 86 note 2 t 83 nmi hold time 1.0 ns 86 note 2 t 84 smi# setup time 5.0 ns 86 note 2 t 85 smi# hold time 1.0 ns 86 note 2 t 86 stpclk# setup time 5.0 ns 86 note 1 t 87 stpclk# hold time 1.0 ns 86 note 1 t 88 wb/wt# setup time 4.5 ns 86 t 89 wb/wt# hold time 1.0 ns 86 table 52. input setup and hold timings for 60-mhz bus operation (continued) symbol parameter description preliminary data figure comments min max notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks.
252 signal switching characteristics chapter 16 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 16.9 reset and test signal timing table 53. reset and configuration signals (60-mhz and 66-mhz operation) symbol parameter description preliminary data figure comments min max t 90 reset setup time 5.0 ns 87 t 91 reset hold time 1.0 ns 87 t 92 reset pulse width, v cc and clk stable 15 clocks 87 t 93 reset active after v cc and clk stable 1.0 ms 87 t 94 bf[2:0] setup time 1.0 ms 87 note 3 t 95 bf[2:0] hold time 2 clocks 87 note 3 t 96 brdyc# hold time 1.0 ns 87 note 4 t 97 brdyc# setup time 2 clocks 87 note 2 t 98 brdyc# hold time 2 clocks 87 note 2 t 99 flush# setup time 5.0 ns 87 note 1 t 100 flush# hold time 1.0 ns 87 note 1 t 101 flush# setup time 2 clocks 87 note 2 t 102 flush# hold time 2 clocks 87 note 2 notes: 1. to be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which reset is sampled negated. 2. if asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of reset. 3. bf[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of reset. 4. if reset is driven synchronously, brdyc# must meet the specified hold time relative to the negation of r eset.
chapter 16 signal switching characteristics 253 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information table 54. tck waveform and trst# timing at 25 mhz symbol parameter description preliminary data figure comments min max tck frequency 25 mhz 88 t 103 tck period 40.0 ns 88 t 104 tck high time 14.0 ns 88 t 105 tck low time 14.0 ns 88 t 106 tck fall time 5.0 ns 88 note 1, 2 t 107 tck rise time 5.0 ns 88 note 1, 2 t 108 trst# pulse width 30.0 ns 89 asynchronous notes: 1. rise/fall times can be increased by 1.0 ns for each 10 mhz that tck is run below its maximum frequency of 25 mhz. 2. rise/fall times are measured between 0.8 v and 2.0 v. table 55. test signal timing at 25 mhz symbol parameter description preliminary data figure notes min max t 109 tdi setup time 5.0 ns 90 note 2 t 110 tdi hold time 9.0 ns 90 note 2 t 111 tms setup time 5.0 ns 90 note 2 t 112 tms hold time 9.0 ns 90 note 2 t 113 tdo valid delay 3.0 ns 13.0 ns 90 note 1 t 114 tdo float delay 16.0 ns 90 note 1 t 115 all outputs (non-test) valid delay 3.0 ns 13.0 ns 90 note 1 t 116 all outputs (non-test) float delay 16.0 ns 90 note 1 t 117 all inputs (non-test) setup time 5.0 ns 90 note 2 t 118 all inputs (non-test) hold time 9.0 ns 90 note 2 notes: 1. parameter is measured from the tck falling edge. 2. parameter is measured from the tck rising edge.
254 signal switching characteristics chapter 16 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 83. diagrams key figure 84. output valid delay timing must be steady can change from high to low can change from low to high (does not apply) dont care, any change permitted steady changing from high to low changing from low to high changing, state unknown center line is high impedance state waveform inputs outputs min max valid n +1 t v valid n clk output signal t x t x 1.5 v v = 6, 8, 10, 12, 14, 15, 17, 18, 20, 22, 24, 26, 27, 28, 29, 30, 32, 34, 36, 37, 39, 41, 42
chapter 16 signal switching characteristics 255 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 85. maximum float delay timing figure 86. input setup and hold timing t x t x t x valid t x t v min output signal t f clk 1.5 v v = 6, 8, 10, 12, 15, 18, 20, 22, 24, 30, 32, 34, 37, 39, 42 f = 7, 9, 11, 13, 16, 19, 21, 23, 25, 31, 33, 35, 38, 40, 43 clk t x t x t x t x input signal t s t h 1.5 v s = 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88 h = 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89
256 signal switching characteristics chapter 16 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 87. reset and configuration timing t x clk reset t x t 90 flush# (synchronous) 1.5 v 1.5 v 1.5 v ? ? ? t 92, 93 t 91 t 99 t 100 ? ? ? bf[2:0] (asynchronous) t 94 ? ? ? t 95 flush#, brdyc# (asynchronous) t 97, 101 t 98, 102 ? ? ? ? ? ?
chapter 16 signal switching characteristics 257 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 88. tck waveform figure 89. trst# timing figure 90. test signal timing diagram t 107 2.0 v 1.5 v 0.8 v t 10 5 t 10 6 t 103 t 10 4 1.5 v t 10 8 tck tdi, tms tdo output signals input signals t 10 3 t 10 9, 111 t 110, 112 t 113 t 115 t 116 t 117 t 118 t 114 1.5 v
258 signal switching characteristics chapter 16 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 17 thermal design 259 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 17 thermal design 17.1 package thermal specifications the amd-k6 processor operating specification calls for the case temperature (t c ) to be in the range of 0c to 70c. the ambient temperature (t a ) is not specified as long as the case temperature is not violated. the case temperature must be measured on the top center of the package. table 56 shows the amd-k6 processor thermal specifications. figure 91 on page 260 shows the thermal model of a processor with a passive thermal solution. the case-to-ambient temperature (t ca ) can be calculated from the following equation: t ca = p max ? q ca = p max ? ( q if + q sa ) where: p max = maximum power consumption q ca = case-to-ambient thermal resistance q if = interface material thermal resistance q sa = sink-to-ambient thermal resistance table 56. package thermal specification t c case temperature q jc junction-case maximum thermal power 2.9v component 3.2v component 166mhz 200mhz 233mhz 0cC70c 0.77c/w 17.2 w 20.0 w 28.3 w stop grant mode 1.45 w 1.53 w 1.75 w stop clock mode 1.0 w 1.0 w 1.0 w
260 thermal design chapter 17 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 91. thermal model figure 92 illustrates the case-to-ambient temperature (t ca ) in relation to the power consumption (x-axis) and the thermal resistance (y-axis). if the power consumption and case temperature are known, the thermal resistance ( q ca ) requirement can be calculated for a given ambient temperature (t a ) value. figure 92. power consumption vs. thermal resistance temperature thermal q sa q ca q if (c/w) (ambient) case sink t ca resistance 0.0 1.0 2.0 3.0 4.0 5.0 6.0 6 w 9 w 12 w 15 w 18 w power consumption (watts) thermal resistance (c/w) 15 c 20 c 25 c 30 c t ca
chapter 17 thermal design 261 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information the following example calculates the required thermal resistance of a heatsink: if: t c = 70c t a = 45c p max = 20.0w at 200mhz then: thermal grease is recommended as interface material because it provides the lowest thermal resistance ( @ 0.20c/w). the required thermal resistance ( q sa ) of the heatsink in this example is calculated as follows: q sa = q ca C q if = 1.25 C 0.20 = 1.05 (c/w) heat dissipation path figure 93 illustrates the processors heat dissipation path. most of the heat generated by the processor is dissipated from the top surface (ceramic and lid) of the package. the small amount of heat generated from the bottom side of the processor where the processor socket blocks the convection can be safely ignored. figure 93. processor heat dissipation path q ca t c t a C p max ------------------- ? ? ?? 25 c 20.0w ----------------- - 1.25 cw () == thin lid case temperature ambient temperature
262 thermal design chapter 17 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information measuring case temperature the case temperature must be measured on the top center of the package where most of the heat is dissipated. figure 94 shows the correct location for measuring the case temperature. (if a heat exchange device is installed, the thermocouple must contact the processor top surface through a drilled hole.) the case temperature is measured to ensure that the thermal solution meets the operational specification. figure 94. measuring case temperature 17.2 layout and airflow considerations voltage regulator a voltage regulator is required to support the lower voltage (3.3 v and lower) to the processor. in most applications, the voltage regulator is designed with power transistors. as a result, additional heatsinks are required to dissipate the heat from the power transistors. figure 95 shows the voltage regulator placed parallel to the processor with the airflow aligned with the devices. with this alignment, the heat generated by the voltage regulator has minimal effect on the processor. thermocouple
chapter 17 thermal design 263 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 95. voltage regulator placement a heatsink and fan combination can deliver much better thermal performance than a heatsink alone. more importantly, with a fan/sink the airflow requirements in a system design are not as critical. a unidirectional heatsink with a fan moves air from the top of the heatsink to the side. in this case, the best location for the voltage regulator is on the side of the processor in the path of the airflow exiting the fan sink (see figure 96). this location guarantees that the heatsinks on both the processor and the regulator receive adequate air circulation. figure 96. airflow for a heatsink with fan processor airflow voltage regulator airflow ideal areas for voltage regulator
264 thermal design chapter 17 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information airflow management in a system design complete airflow management in a system is important. in addition to the volume of air, the path of the air is also important. figure 97 shows the airflow in a dual-fan system. the fan in the front end pulls cool air into the system through intake slots in the chassis. the power supply fan forces the hot air out of the chassis. the thermal performance of the heatsink can be maximized if it is located in the shaded area, where it receives greatest benefit from this air exchange system. figure 97. airflow path in a dual-fan system drive bays p/s vents v e n t s fan fan main board front
chapter 17 thermal design 265 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 98 shows the airflow management in a system using the atx form-factor. the orientation of the power supply fan and the motherboard are modified in the atx platform design. the power supply fan pulls cool air through the chassis and across the processor. the processor is located near the power supply fan, where it can receive adequate airflow without an auxiliary fan. the arrangement significantly improves the airflow across the processor with minimum installation cost. figure 98. airflow path in an atx form-factor system for more information about thermal solutions, see the amd-k6 ? processor thermal solution design application note , order# 21085. p/s main board drive bays f a n
266 thermal design chapter 17 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 18 pin description diagram 267 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 18 pin description diagram figure 99. amd-k6 ? processor top-side view
268 pin description diagram chapter 18 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 100. amd-k6 ? processor pin-side view
chapter 19 pin designations 269 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 19 pin designations amd-k6 ? processor model 6 functional grouping address data control test nc v cc2 v cc3 v ss pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin no. pin no. pin no. pin no. a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 al-35 am-34 ak-32 an-33 al-33 am-32 ak-30 an-31 al-31 al-29 ak-28 al-27 ak-26 al-25 ak-24 al-23 ak-22 al-21 af-34 ah-36 ae-33 ag-35 aj-35 ah-34 ag-33 ak-36 ak-34 am-36 aj-33 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d32 d33 d34 d35 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 k-34 g-35 j-35 g-33 f-36 f-34 e-35 e-33 d-34 c-37 c-35 b-36 d-32 b-34 c-33 a-35 b-32 c-31 a-33 d-28 b-30 c-29 a-31 d-26 c-27 c-23 d-24 c-21 d-22 c-19 d-20 c-17 c-15 d-16 c-13 d-14 c-11 d-12 c-09 d-10 d-08 a-05 e-09 b-04 d-06 c-05 e-07 c-03 d-04 e-05 d-02 f-04 e-03 g-05 e-01 g-03 h-04 j-03 j-05 k-04 l-05 l-03 m-04 n-03 a20m# ads# adsc# ahold apchk# be0# be1# be2# be3# be4# be5# be6# be7# bf0 bf1 bf2 boff# brdy# brdyc# breq cache# clk d/c# eads# ewbe# ferr# flush# hit# hitm# hlda hold ignne# init intr inv ken# lock# m/io# na# nmi pcd pchk# pwt reset scyc smi# smiact# stpclk# vcc2det w/r# wb/wt# ak-08 aj-05 am-02 v-04 ae-05 al-09 ak-10 al-11 ak-12 al-13 ak-14 al-15 ak-16 y-33 x-34 w-35 z-04 x-04 y-03 aj-01 u-03 ak-18 ak-04 am-04 w-03 q-05 an-07 ak-06 al-05 aj-03 ab-04 aa-35 aa-33 ad-34 u-05 w-05 ah-04 t-04 y-05 ac-33 ag-05 af-04 al-03 ak-20 al-17 ab-34 ag-03 v-34 al-01 am-06 aa-05 tck m-34 tdi n-35 tdo n-33 tms p-34 trst# q-33 parity ap ak-02 dp0 d-36 dp1 d-30 dp2 c-25 dp3 d-18 dp4 c-07 dp5 f-06 dp6 f-02 dp7 n-05 a-37 e-17 e-25 r-34 s-33 s-35 w-33 aj-15 aj-23 al-19 an-35 inc c-01 h-34 y-35 z-34 ac-35 al-07 an-01 an-03 an-05 rsvd j-33 l-35 p-04 q-03 q-35 r-04 s-03 s-05 aa-03 ac-03 ac-05 ad-04 ae-03 ae-35 key ah-32 a-07 a-09 a-11 a-13 a-15 a-17 b-02 e-15 g-01 j-01 l-01 n-01 q-01 s-01 u-01 w-01 y-01 aa-01 ac-01 ae-01 ag-01 aj-11 an-09 an-11 an-13 an-15 an-17 an-19 a-19 a-21 a-23 a-25 a-27 a-29 e-21 e-27 e-37 g-37 j-37 l-33 l-37 n-37 q-37 s-37 t-34 u-33 u-37 w-37 y-37 aa-37 ac-37 ae-37 ag-37 aj-19 aj-29 an-21 an-23 an-25 an-27 an-29 a-03 am-20 b-06 am-22 b-08 am-24 b-10 am-26 b-12 am-28 b-14 am-30 b-16 an-37 b-18 b-20 b-22 b-24 b-26 b-28 e-11 e-13 e-19 e-23 e-29 e-31 h-02 h-36 k-02 k-36 m-02 m-36 p-02 p-36 r-02 r-36 t-02 t-36 u-35 v-02 v-36 x-02 x-36 z-02 z-36 ab-02 ab-36 ad-02 ad-36 af-02 af-36 ah-02 aj-07 aj-09 aj-13 aj-17 aj-21 aj-25 aj-27 aj-31 aj-37 al-37 am-08 am-10 am-12 am-14 am-16 am-18
270 pin designations chapter 19 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 20 package specifications 271 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 20 package specifications 20.1 321-pin staggered cpga package specification table 57. 321-pin staggered cpga package specification symbol millimeters inches min max notes min max notes a 49.28 49.78 1.940 1.960 b 45.59 45.85 1.795 1.805 c 31.32 32.59 1.233 1.283 d 44.90 45.10 1.768 1.776 e 2.91 3.63 0.115 0.143 f 1.30 1.52 0.051 0.060 g 3.05 3.30 0.120 0.130 h 0.43 0.51 0.017 0.020 m 2.29 2.79 0.090 0.110 n 1.14 1.40 0.045 0.055 d 1.52 2.29 0.060 0.090 e 1.52 2.54 0.060 0.100 f 0.13 flatness 0.005 flatness
272 package specifications chapter 20 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 101. 321-pin staggered cpga package specification
chapter 21 ordering information 273 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 21 ordering information standard products amd standard products are available in several operating ranges. the ordering part number (opn) is formed by a combination of the elements below. table 58. valid ordering part number combinations opn package type operating voltage case temperature amd-k6-233anr 321-pin cpga 3.1vC3.3v (core) 3.135vC3.6v (i/o) 0cC70c amd-k6-200alr 321-pin cpga 2.755vC3.045v (core) 3.135vC3.6v (i/o) 0cC70c AMD-K6-166ALR 321-pin cpga 2.755vC3.045v (core) 3.135vC3.6v (i/o) 0cC70c notes: this table lists configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly-released combinations. a amd-k6 package type family/core a = 321-pin cpga amd-k6 case temperature r= 0cC70c -233 performance rating -233 -200 -166 operating voltage n = 3.1 vC3.3 v (core) / 3.135 vC3.6 v (i/o) l = 2.755 vC3.045 v (core) / 3.135 vC3.6 v (i/o) n r
274 ordering information chapter 21 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
20695h/0march 1998 amd-k6 ? processor data sheet preliminary information part two amd-k6 ? processor model 7 275 part two amd-k6 processor model 7 the amd-k6 ? processor data sheet supports the model 6 and model 7 versions of the amd-k6 processor family. model 6 refers to the amd-k6 manufactured with 0.35-micron process technology and model 7 refers to the amd-k6 manufactured with 0.25-micron process technology. part two (chapters 22C42) contains information regarding new specifications and differences that pertain only to model 7 as compared to model 6. ?
276 amd-k6 ? processor model 7 part two amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 22 amd-k6 ? processor 277 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 22 amd-k6 ? processor n advanced 6-issue risc86 ? superscalar microarchitecture u seven parallel specialized execution units u multiple sophisticated x86-to-risc86 instruction decoders u advanced two-level branch prediction u speculative execution u out-of-order execution u register renaming and data forwarding u issues up to six risc86 instructions per clock n large on-chip split 64-kbyte level-one (l1) cache u 32-kbyte instruction cache with additional predecode cache u 32-kbyte writeback dual-ported data cache u mesi protocol support n high-performance ieee 754-compatible and 854-compatible floating-point unit n high-performance industry-standard mmx? instructions n 321-pin ceramic pin grid array (cpga) package (socket 7 compatible) n industry-standard system management mode (smm) n ieee 1149.1 boundary scan n full x86 binary software compatibility n 0.25-micron process technology amd continues to deliver leading-edge processor solutions by advancing the highly successful amd-k6 ? processor with state-of-the-art 0.25-micron process technology. the amd-developed 0.25-micron process technology enables the amd-k6 processor to deliver higher performance with a lower core voltage and lower power dissipation. this new version of the amd-k6 processor continues to leverage todays cost-effective infrastructure to deliver a superior price/performance pc solution. to provide industry-leading performance, the amd-k6 processor incorporates the innovative and efficient risc86 microarchitecture, a large 64-kbyte level-one cache (32-kbyte dual-ported data cache, 32-kbyte instruction cache with predecode data), a powerful ieee 754-compatible and 854-compatible floating-point execution unit, and a high-performance multimedia execution unit for executing industry-standard mmx instructions. these features have been combined to deliver industry leadership in 16-bit and 32-bit performance, providing exceptional performance for both windows ? 95 and windows nt? software bases.
278 amd-k6 ? processor chapter 22 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information the amd-k6 processors risc86 microarchitecture is a decoupled decode/execution superscalar design that implements state-of-the-art design techniques to achieve leading-edge performance. advanced design techniques implemented in the amd-k6 include multiple x86 instruction decode, single-clock internal risc operations, seven execution units that support superscalar operation, out-of-order execution, data forwarding, speculative execution, and register renaming. in addition, the processor supports the industrys most advanced branch prediction logic by implementing an 8192-entry branch history table, the industrys only branch target cache, and a return address stack, which combine to deliver better than a 95% prediction rate. these design techniques enable the amd-k6 processor to issue, execute, and retire multiple x86 instructions per clock, resulting in excellent scaleable performance. the amd-k6 processor is fully x86 binary code compatible. amds extensive experience through four generations of x86 processors has been carefully integrated into the amd-k6 to provide complete compatibility with windows 95, windows 3.x, windows nt, dos, os/2, unix, solaris, netware ? , vines, and other leading x86 operating systems and applications. the amd-k6 processor is socket 7 compatible, allowing the processor to be quickly and easily integrated into a mature and cost-effective industry-standard infrastructure of motherboards, chipsets, power supplies, and thermal designs. amd has designed, manufactured, and delivered over 50 million microsoft windows-compatible processors in the last five years alone. the amd-k6 processor is the next addition to this long line of processors. with its combination of state-of-the-art features, industry-leading performance, high-performance multimedia engine, full x86 compatibility, and low-cost infrastructure, the amd-k6 is the superior choice for mainstream personal computers.
chapter 23 internal architecture 279 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 23 internal architecture the internal architecture of the amd-k6 processor remains unchanged with the integration of 0.25-micron process technology. for information about the internal architecture of the amd-k6 processor model 7, see chapter 2, internal architecture on page 7.
280 internal architecture chapter 23 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 24 software environment 281 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 24 software environment this chapter briefly describes the amd-k6 model-specific registers (msrs) and x86 instructions supported by the amd-k6 processor model 7 that are not supported by the amd-k6 processor model 6. for an overview of the amd-k6 processors x86 software environment and a description of the remaining data types, registers, operating modes, interrupts, and instructions supported by the amd-k6 architecture and design implementation, see chapter 3, software environment on page 21. 24.1 registers the amd-k6 processor contains all the registers defined by the x86 architecture, including general-purpose, segment, floating-point, mmx, eflags, control, task, debug, test, and descriptor/memory-management registers. this section provides information on the model-specific registers (msrs) supported by the amd-k6 processor model 7 that are not supported by the amd-k6 processor model 6. for information about the remaining amd-k6 registers, see chapter 3, software environment on page 21. note: areas of the register designated as reserved should not be modified by software. model-specific registers (msr) the amd-k6 processor model 7 supports two additional msrs as compared to the amd-k6 processor model 6. the value in the ecx register selects the msr to be addressed by the rdmsr and wrmsr instructions. the values in eax and edx are used as inputs and outputs by the rdmsr and wrmsr instructions. table 59 lists the new msrs and the corresponding value of the ecx register. figures 102 and 103 show the msr formats.
282 software environment chapter 24 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information for more information about the rdmsr and wrmsr instructions, see the amd k86? family bios and software tools development guide , order# 21062. extended feature enable register (efer). the extended feature enable register (efer) contains the control bits that enable the extended features of the amd-k6. figure 102 shows the format of the efer register, and table 60 defines the function of each bit in the efer register. figure 102. extended feature enable register (efer) syscall/sysret target address register (star). the syscall/sysret target address register (star) contains the target eip address used by the syscall instruction and the 16-bit code and stack segment selector bases used by the syscall and sysret instructions. figure 103 shows the format of the star register, and table 61 defines the function of each bit of the star register. for more information, see the syscall and sysret instruction specification application note , order# 21086. table 59. model-specific registers (msrs) model-specific register value of ecx extended feature enable register (efer) c000_0080h syscall/sysret target address register (star) c000_0081h 10 63 s c e reserved symbol description b it sce system call/return extension 0 table 60. extended feature enable register (efer) definition bit description r/w 63C1 reserved r 0 system call/return extension (sce) r/w
chapter 24 software environment 283 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information figure 103. syscall/sysret target address register (star) 24.2 instructions supported by the amd-k6 ? processor this section documents the x86 instructions supported by the amd-k6 processor model 7 that are not supported by amd-k6 processor model 6. for information about the remaining x86 instructions supported by the amd-k6 processor model 6, see chapter 3, software environment on page 21. table 62 shows the instruction mnemonic, opcode, modr/m byte, decode type, and risc86 operation(s) for each instruction. the first column of the tables indicates the instruction mnemonic and operand types. the second and third columns list all applicable opcode bytes. the fourth column lists the modr/m byte when used by the instruction. the modr/m byte defines the instruction as a register or memory form. the fifth column lists the type of instruction decode short, long, and vector. the sixth column lists the type of risc86 operation(s) required for the instruction. 31 0 63 target eip address 32 47 48 syscall cs selector and ss selector base sysret cs selector and ss selector base table 61. syscall/sysret target address register (star) definition bit description r/w 63C48 sysret cs and ss selector base r/w 47C32 syscall cs and ss selector base r/w 31C0 target eip address r/w table 62. integer instructions instruction mnemonic first byte second byte modr/m byte decode type risc86 ? opcodes syscall 0fh 05h vector sysret 0fh 07h vector
284 software environment chapter 24 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 25 logic symbol diagram 285 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 25 logic symbol diagram a20m# a[31:3] ap ads# adsc# apchk# be[7:0]# ahold boff# breq hlda hold d/c# ewbe# lock# m/io# na# scyc w/r# cache# ken# pcd pwt wb/wt# clock bus arbitration clk bf[2:0] tck tdi tdo tms trst# brdy# brdyc# d[63:0] dp[7:0] pchk# eads# hit# hitm# inv ferr# ignne# flush# init intr nmi reset smi# smiact# stpclk# jtag test data and data parity inquire cycles floating-point error handling external interrupts, smm, reset and initialization address and address parity cycle definition and control cache control amd-k6 ? processor model 7 voltage detection vcc2det vcc2h/l#
286 logic symbol diagram chapter 25 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 26 signal descriptions 287 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 26 signal descriptions this chapter provides a description of the signals designed to indicate to system logic the specified dual-voltage requirements of the amd-k6 processor model 7. for information about the remaining amd-k6 processor model 7 signals, see chapter 5, signal descriptions on page 79. 26.1 vcc2det (v cc2 detect) output summary vcc2det is internally tied to v ss (logic level 0) to indicate to the system logic that it must supply the specified dual-voltage requirements to the v cc2 and v cc3 pins. the v cc2 pins supply voltage to the processor core, independent of the voltage supplied to the i/o buffers on the v cc3 pins. upon sampling vcc2det low, system logic should sample vcc2h/l# to identify core voltage requirements. driven vcc2det always equals 0 and is never floatedeven during tri-state test mode. 26.2 vcc2h/l# (v cc2 high/low) output summary vcc2h/l# is internally tied to v ss (logic level 0) to indicate to the system logic that it must supply the specified processor core voltage to the v cc2 pins. the v cc2 pins supply voltage to the processor core, independent of the voltage supplied to the i/o buffers on the v cc3 pins. upon sampling vcc2det low to identify dual-voltage processor requirements, system logic should sample vcc2h/l# to identify the core voltage requirements for 2.9v and 3.2v products (high) and 2.2v products (low). driven vcc2h/l# always equals 0 and is never floated for 2.2v productseven during tri-state test mode. to ensure proper
288 signal descriptions chapter 26 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information operation for 2.9v and 3.2v products, system logic that samples vcc2h/l# should design a weak pullup resistor for this signal. table 63. output pin float conditions name floated at: note vcc2det always driven * vcc2h/l# always driven * notes: * all outputs except vcc2det, vcc2h/l#, and tdo float during tri-state test mode.
chapter 27 bus cycles 289 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 27 bus cycles the timing and relationship of bus signals for the amd-k6 processor remain unchanged with the integration of 0.25-micron process technology. for information about bus cycles for the amd-k6 processor model 7, see chapter 6, bus cycles on page 121.
290 bus cycles chapter 27 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 28 power-on configuration and initialization 291 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 28 power-on configuration and initialization this chapter provides information on the power-on configuration and initialization states of the amd-k6 processor model 7 that differ from the states of the amd-k6 processor model 6. for more information about the power-on configuration and initialization states of the amd-k6 processor model 7, see chapter 7, power-on configuration and initialization on page 167. 28.1 state of processor after reset output signals table 64 shows the state of processor outputs immediately after reset is sampled asserted. the processor outputs shown are those supported by the amd-k6 processor model 7 that are not supported by the outputs of the amd-k6 processor model 6. for information about the state of the remaining processor outputs after reset for the amd-k6 processor model 7, see chapter 7, power-on configuration and initialization on page 167. table 65 on page 292 shows the state of the architecture register edx and the model-specific registers efer and star after the processor has completed its initialization due to the recognition of reset. edx is supported in both the amd-k6 processor model 7 and amd-k6 processor model 6. efer and star are supported only in the amd-k6 processor model 7. table 64. output signal state after reset signal state vcc2h/l# low
292 power-on configuration and initialization chapter 28 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information table 65. register state after reset register state (hex) notes edx 0000_057xh 1 efer 0000_0000_0000_0000h 2 star 0000_0000_0000_0000h 2 notes: 1. edx contains the amd-k6 processor signature, where x indicates the processor stepping id. 2. the contents of these registers are preserved following the recognition of init.
chapter 29 cache organization 293 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 29 cache organization the internal cache organization of the amd-k6 processor remains unchanged with the integration of 0.25-micron process technology. for information about the cache organization of the amd-k6 processor model 7, see chapter 8, cache organization on page 171.
294 cache organization chapter 29 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 30 floating-point and multimedia execution units 295 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 30 floating-point and multimedia execution units the floating-point and multimedia execution units of the amd-k6 processor remain unchanged with the integration of 0.25-micron process technology. for information about the floating-point and multimedia execution units of the amd-k6 processor model 7, see chapter 9, floating-point and multimedia execution units on page 189.
296 floating-point and multimedia execution units chapter 30 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 31 system management mode (smm) 297 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 31 system management mode (smm) the implementation of smm in the amd-k6 processor remains unchanged with the integration of 0.25-micron process technology. for information about the implementation of smm in the amd-k6 processor model 7, see chapter 10, system management mode (smm) on page 193.
298 system management mode (smm) chapter 31 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 32 test and debug 299 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 32 test and debug the amd-k6 processor implements various test and debug modes to enable the functional and manufacturing testing of systems and boards that use the processor. in addition, the debug features of the processor allow designers to debug the instruction execution of software components. this chapter describes the following test and debug features of the amd-k6 processor model 7 that differ from those supported by the amd-k6 processor model 6: n tri-state test mode a test mode that causes the processor to float its output and bidirectional pins. n boundary-scan test access port (tap) the joint test action group (jtag) test access function defined by the ieee standard test access port and boundary-scan architecture (ieee 1149.1-1990) specification. for more information about the test and debug modes of the amd-k6 processor model 7, see chapter 11, test and debug on page 203. 32.1 tri-state test mode the vcc2det, vcc2h/l#, and tdo signals are the only outputs not floated in the tri-state test mode. vcc2det and vcc2h/l# must remain low to ensure the system continues to supply the specified processor core voltage to the v cc2 pins. tdo is never floated because the boundary-scan test access port must remain enabled at all times, including during the tri-state test mode. the tri-state test mode is exited when the processor samples reset asserted. 32.2 boundary-scan test access port (tap) the boundary-scan test access port (tap) is an ieee standard that defines synchronous scanning test methods for complex logic circuits, such as boards containing a processor. the amd-k6 processor supports the tap standard defined in the
300 test and debug chapter 32 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information ieee standard test access port and boundary-scan architecture (ieee 1149.1-1990) specification. tap registers device identification register (dir). the dir is a 32-bit test data register selected during the execution of the idcode instruction. the fields of the dir and their values are shown in table 66 and are defined as follows: n version code this 4-bit field is incremented by amd manufacturing for each major revision of silicon. n part number this 16-bit field identifies the specific processor model. n manufacturer this 11-bit field identifies the manufacturer of the component (amd). n lsb the least significant bit (lsb) of the dir is always set to 1, as specified by the ieee 1149.1 standard. table 66. device identification register version code (bits 31C28) part number (bits 27C12) manufacturer (bits 11C1) lsb (bit 0) xh 0570h 00000000001b 1b
chapter 33 clock control 301 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 33 clock control the clock control modes of the amd-k6 processor remain unchanged with the integration of 0.25-micron process technology. for information about the clock control modes of the amd-k6 processor model 7, see chapter 12, clock control on page 223.
302 clock control chapter 33 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 34 power and grounding 303 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 34 power and grounding the fundamental power and ground requirements of the amd-k6 processor remain unchanged with the integration of 0.25-micron process technology. for information about decoupling recommendations and pin connection requirements of the amd-k6 processor model 7, see the amd-k6 ? processor power supply design application note, order# 21103 and chapter 13, power and grounding on page 229 . 34.1 power connections the amd-k6 processor is a dual voltage device. two separate supply voltages are requiredv cc2 and v cc3 . v cc2 provides the core voltage for the processor and v cc3 provides the i/o voltage. see electrical data on page 233 for the value and range of v cc2 and v cc3 . there are 28 v cc2 , 32 v cc3 , and 68 v ss pins on the amd-k6 processor. (see pin designations on page 269 for all power and ground pin designations.) the large number of power and ground pins are provided to ensure that the processor and package maintain a clean and stable power distribution network. for more information about power connections requirements for the amd-k6 processor model 7, see chapter 13, power and grounding on page 229.
304 power and grounding chapter 34 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 35 electrical data 305 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 35 electrical data 35.1 operating ranges the functional operation of the amd-k6 processor model 7 is guaranteed if the voltage and temperature parameters are within the limits defined in table 67. 35.2 absolute ratings functional operation of the amd-k6 processor model 7 is not guaranteed beyond the operating ranges listed in table 67. exposure to conditions outside these operating ranges for extended periods of time can affect long-term reliability. permanent damage can occur if the absolute ratings listed in table 68 are exceeded. table 67. operating ranges parameter minimum typical maximum comments v cc2 2.1 v 2.2 v 2.3 v note 1, 2 v cc3 3.135 v 3.30 v 3.6 v note 1 t case 0 c70 c notes: 1. v cc2 and v cc3 are referenced from v ss . 2. v cc2 specification for 2.2 v components. table 68. absolute ratings parameter minimum maximum comments v cc2 C0.5 v 2.5 v v cc3 C0.5 v 3.6 v v pin C0.5 v v cc3 + 0.5 v and 4.0 v note t case (under bias) C65 c +110 c t storage C65 c +150 c note: v pin (the voltage on any i/o pin) must not be greater than 0.5 v above the voltage being applied to v cc3 . in addition, the v pin voltage must never exceed 4.0 v.
306 electrical data chapter 35 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information 35.3 dc characteristics the dc characteristics of the amd-k6 processor model 7 are shown in table 69. table 69. dc characteristics symbol parameter description preliminary data comments min max v il input low voltage C0.3 v +0.8 v v ih input high voltage 2.0 v v cc3 +0.3v note 1 v ol output low voltage 0.4 v i ol = 4.0-ma load v oh output high voltage 2.4 v i oh = 3.0-ma load i cc2 2.2 v power supply current 5.95 a 200 mhz, note 2 6.50 a 233 mhz, note 2 7.05 a 266 mhz, note 2 7.49 a 300 mhz, note 2 i cc3 3.3 v power supply current 0.50 a 200 mhz, note 3 0.52 a 233 mhz, note 3 0.54 a 266 mhz, note 3 0.56 a 300 mhz, note 3 i li input leakage current 15 m anote 4 i lo output leakage current 15 m anote 4 i il input leakage current bias with pullup C400 m anote 5 i ih input leakage current bias with pulldown 200 m anote 6 c in input capacitance 10 pf c out output capacitance 15 pf c out i/o capacitance 20 pf c clk clk capacitance 10 pf c tin test input capacitance (tdi, tms, trst#) 10 pf c tout test output capacitance (tdo) 15 pf c tck tck capacitance 10 pf notes: 1. v cc3 refers to the voltage being applied to v cc3 during functional operation. 2. v cc2 = 2.3 v the maximum power supply current must be taken into account when designing a power supply. 3. v cc3 = 3.6 v the maximum power supply current must be taken into account when designing a power supply. 4. refers to inputs and i/o without an internal pullup resistor and 0 v in v cc3. 5. refers to inputs with an internal pullup and v il = 0.4 v. 6. refers to inputs with an internal pulldown and v ih = 2.4 v.
chapter 35 electrical data 307 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 35.4 power dissipation table 70 contains the typical and maximum power dissipation of the amd-k6 processor model 7 during normal and reduced power states. table 70. typical and maximum power dissipation clock control state 2.2 v component comments 200 mhz 233 mhz 266 mhz 300 mhz normal (maximum thermal power) 12.45 w 13.50 w 14.55 w 15.40 w note 1, 2 normal (typical thermal power) 7.50 w 8.10 w 8.75 w 9.25 w note 3 stop grant / halt (maximum) 2.44 w 2.46 w 2.48 w 2.50 w note 4 stop clock (maximum) 2.25 w 2.25 w 2.25 w 2.25 w note 5 notes: 1. the maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal dissipation for the amd-k6 processor. 2. maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with v cc2 = 2.2 v and v cc3 = 3.3 v. 3. typical power is determined for the typical instruction sequences or functions associated with normal system operation with v cc2 = 2.2 v and v cc3 = 3.3 v. 4. the clk signal and the internal pll are still running but most internal clocking has stopped. 5. the clk signal, the internal pll, and all internal clocking has stopped.
308 electrical data chapter 35 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 36 i/o buffer characteristics 309 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 36 i/o buffer characteristics the i/o buffer characteristics of the amd-k6 processor model 7 are different from those of the amd-k6 processor model 6. these differences are minor and are reflected in the i/o buffer ibis models that are developed for each processor. for the ibis models and their application, refer to the amd-k6 ? processor i/o model application note , order# 21084. despite these minor differences, the ac timing specifications and the dc specifications of the i/o buffers remain unchanged with the integration of 0.25-micron process technology. for additional information about the i/o buffer characteristics of the amd-k6 processor model 7, see chapter 15, i/o buffer characteristics on page 237.
310 i/o buffer characteristics chapter 36 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 37 signal switching characteristics 311 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 37 signal switching characteristics the signal switching characteristics of the amd-k6 processor remain unchanged with the integration of 0.25-micron process technology. for information about the signal switching characteristics of the amd-k6 processor model 7, see chapter 16, signal switching characteristics on page 241.
312 signal switching characteristics chapter 37 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 38 thermal design 313 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 38 thermal design 38.1 package thermal specifications the amd-k6 processor model 7 operating specification calls for the case temperature (t c ) to be i n the range of 0c to 70c. the ambient temperature (t a ) is not specified as long as the case temperature is not violated. the case temperature must be measured on the top center of the package. table 71 shows the amd-k6 processor thermal specifications. for information about thermal solutions, see the amd-k6 ? processor thermal solution design application note , order# 21085. table 71. package thermal specification t c case temperature q jc junction-case maximum thermal power 2.2 v component 200 mhz 233 mhz 266 mhz 300 mhz 0cC70c 1.7 c/w 12.45 w 13.50 w 14.55 w 15.40 w stop grant mode 2.44 w 2.46 w 2.48 w 2.50 w stop clock mode 2.25 w 2.25 w 2.25 w 2.25 w
314 thermal design chapter 38 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 39 pin description diagram 315 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 39 pin description diagram figure 104. amd-k6 ? processor model 7 top-side view
316 pin description diagram chapter 39 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information figure 105. amd-k6 ? processor model 7 pin-side view
chapter 40 pin designations 317 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 40 pin designations amd-k6 ? processor model 7 functional grouping address data control test nc v cc2 v cc3 v ss pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin no. pin no. pin no. pin no. a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 al-35 am-34 ak-32 an-33 al-33 am-32 ak-30 an-31 al-31 al-29 ak-28 al-27 ak-26 al-25 ak-24 al-23 ak-22 al-21 af-34 ah-36 ae-33 ag-35 aj-35 ah-34 ag-33 ak-36 ak-34 am-36 aj-33 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d32 d33 d34 d35 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 k-34 g-35 j-35 g-33 f-36 f-34 e-35 e-33 d-34 c-37 c-35 b-36 d-32 b-34 c-33 a-35 b-32 c-31 a-33 d-28 b-30 c-29 a-31 d-26 c-27 c-23 d-24 c-21 d-22 c-19 d-20 c-17 c-15 d-16 c-13 d-14 c-11 d-12 c-09 d-10 d-08 a-05 e-09 b-04 d-06 c-05 e-07 c-03 d-04 e-05 d-02 f-04 e-03 g-05 e-01 g-03 h-04 j-03 j-05 k-04 l-05 l-03 m-04 n-03 a20m# ads# adsc# ahold apchk# be0# be1# be2# be3# be4# be5# be6# be7# bf0 bf1 bf2 boff# brdy# brdyc# breq cache# clk d/c# eads# ewbe# ferr# flush# hit# hitm# hlda hold ignne# init intr inv ken# lock# m/io# na# nmi pcd pchk# pwt reset scyc smi# smiact# stpclk# vcc2det vcc2h/l# w/r# wb/wt# ak-08 aj-05 am-02 v-04 ae-05 al-09 ak-10 al-11 ak-12 al-13 ak-14 al-15 ak-16 y-33 x-34 w-35 z-04 x-04 y-03 aj-01 u-03 ak-18 ak-04 am-04 w-03 q-05 an-07 ak-06 al-05 aj-03 ab-04 aa-35 aa-33 ad-34 u-05 w-05 ah-04 t-04 y-05 ac-33 ag-05 af-04 al-03 ak-20 al-17 ab-34 ag-03 v-34 al-01 an-05 am-06 aa-05 tck m-34 tdi n-35 tdo n-33 tms p-34 trst# q-33 parity ap ak-02 dp0 d-36 dp1 d-30 dp2 c-25 dp3 d-18 dp4 c-07 dp5 f-06 dp6 f-02 dp7 n-05 a-37 e-17 e-25 r-34 s-33 s-35 w-33 aj-15 aj-23 al-19 an-35 inc c-01 h-34 y-35 z-34 ac-35 al-07 an-01 an-03 rsvd j-33 l-35 p-04 q-03 q-35 r-04 s-03 s-05 aa-03 ac-03 ac-05 ad-04 ae-03 ae-35 key ah-32 a-07 a-09 a-11 a-13 a-15 a-17 b-02 e-15 g-01 j-01 l-01 n-01 q-01 s-01 u-01 w-01 y-01 aa-01 ac-01 ae-01 ag-01 aj-11 an-09 an-11 an-13 an-15 an-17 an-19 a-19 a-21 a-23 a-25 a-27 a-29 e-21 e-27 e-37 g-37 j-37 l-33 l-37 n-37 q-37 s-37 t-34 u-33 u-37 w-37 y-37 aa-37 ac-37 ae-37 ag-37 aj-19 aj-29 an-21 an-23 an-25 an-27 an-29 a-03 am-20 b-06 am-22 b-08 am-24 b-10 am-26 b-12 am-28 b-14 am-30 b-16 an-37 b-18 b-20 b-22 b-24 b-26 b-28 e-11 e-13 e-19 e-23 e-29 e-31 h-02 h-36 k-02 k-36 m-02 m-36 p-02 p-36 r-02 r-36 t-02 t-36 u-35 v-02 v-36 x-02 x-36 z-02 z-36 ab-02 ab-36 ad-02 ad-36 af-02 af-36 ah-02 aj-07 aj-09 aj-13 aj-17 aj-21 aj-25 aj-27 aj-31 aj-37 al-37 am-08 am-10 am-12 am-14 am-16 am-18
318 pin designations chapter 40 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 41 package specifications 319 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 41 package specifications the package specifications for the amd-k6 processor remain unchanged with the integration of 0.25-micron process technology. for information about the package specifications of the amd-k6 processor model 7, see chapter 20, package specifications on page 271.
320 package specifications chapter 41 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
chapter 42 ordering information 321 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information 42 ordering information standard amd-k6 ? processor model 7 products amd standard products are available in several operating ranges. the ordering part number (opn) is formed by a combination of the elements below. table 72. valid ordering part number combinations opn package type operating voltage case temperature amd-k6/300afr 321-pin cpga 2.1 vC2.3v (core) 3.135vC3.6v (i/o) 0cC70c amd-k6/266afr 321-pin cpga 2.1vC2.3v (core) 3.135vC3.6v (i/o) 0cC70c amd-k6/233afr 321-pin cpga 2.1vC2.3v (core) 3.135vC3.6v (i/o) 0cC70c amd-k6/200afr 321-pin cpga 2.1vC2.3v (core) 3.135vC3.6v (i/o) 0cC70c notes: this table lists configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly-released combinations. a amd-k6 package type family/core a = 321-pin cpga amd-k6 case temperature r= 0cC70c /300 performance rating /300 /266 /233 /200 operating voltage f = 2.1 vC2.3 v (core) / 3.135 vC3.6 v (i/o) f r
322 ordering information chapter 42 amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information
index 323 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information index numerics 0.25-micron process technology . . . . . . . . . . . . . . . . . 1 , 3 , 275 0.35-micron process technology . . . . . . . . . . . . . . . . . 1 , 3 , 275 321-pin staggered cpga package specification. . . . . . . . 271 60-mhz bus clock switching characteristics . . . . . . . . . . . . . . . . . . . . 242 input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 250 output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 66-mhz bus clock switching characteristics . . . . . . . . . . . . . . . . . . . . 242 input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 246 output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 a a[20:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 C 238 a[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 a20m# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 , 194 a20m# masking of cache accesses . . . . . . . . . . . . . . . . . . 187 absolute ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 , 305 acknowledge, interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 address bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 stack, return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 address bus . . . . . . . . . . . 81 C 85 , 94 , 121 , 142 , 146 , 148 , 183 ads# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 , 237 C 238 adsc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ahold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 , 224 -initiated inquire hit to modified line. . . . . . . . . . . . . . . 146 -initiated inquire hit to shared or exclusive line . . . . . . 144 -initiated inquire miss . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 airflow consideration, layout and . . . . . . . . . . . . . . . . . . . 262 airflow management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 allocate, write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 amd-k6 mmx enhanced processor . . . . . . . . . . . . . . . . 5 , 277 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 instructions supported . . . . . . . . . . . . . . . . . . . . . . . . 49 , 283 microarchitecture overview . . . . . . . . . . . . . . . . . . . . . . . . . 7 model 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 3 , 275 model 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 3 , 275 ap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 apchk#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 application note, i/o model . . . . . . . . . . . . . . . . . . . . . . . . 239 architecture, internal . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 279 b backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 base address, smm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 be[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 bf[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 , 167 , 227 bist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 bits, predecode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 , 172 block diagram, amd-k6 processor . . . . . . . . . . . . . . . . . . . 10 boff# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 , 150 locked operation with . . . . . . . . . . . . . . . . . . . . . . . . . . 154 boundary scan register (bsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . 205 , 299 br . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 branch execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 history table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 prediction . . . . . . . . . . . . . . . . . . . . . . . 5 C 6 , 9 , 20 , 277 C 278 prediction logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 C 19 target cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 brdy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 brdyc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 , 167 , 237 breq. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 bsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 buffer characteristics, i/o . . . . . . . . . . . . . . . . . . . . . 237 , 309 buffer model, i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 built-in self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 burst reads, pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 burst ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 burst ready copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 , 167 burst writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 bus address . . . . . . . . . . . . . 82 C 85 , 94 , 121 , 142 , 146 , 148 , 183 arbitration cycles, inquire and . . . . . . . . . . . . . . . . . . . . 136 backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 , 289 cycles, special. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 data . . . . . . . . . . . . . . . . . . . . . . 82 , 85 , 88 , 92 C 93 , 108 , 111 . . . . . . . . . . . . . . . . . . . . . . . . . .124 C 126 , 142 , 148 , 152 enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 hold request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 state machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 123 bus states address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 data-na# requested . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 idle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 pipeline address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 pipeline data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 bypass instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 c cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 branch target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 flush. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
324 index amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information inhibit, l1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 mesi states in the data . . . . . . . . . . . . . . . . . . . . . . . . . . 172 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 , 293 snooping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 C 11 cache# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 , 175 cacheable access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 cacheable page, write to a . . . . . . . . . . . . . . . . . . . . . . . . . 178 cache-line fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 , 184 cache-related signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 capture-dr state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 capture-ir state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 centralized scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 characteristics i/o buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 , 309 i/o buffer ac and dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 clock control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 , 301 clock states halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 stop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 , 226 C 227 stop grant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 , 225 stop grant inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 coherency states, writethrough vs. writeback. . . . . . . . . 187 coherency, cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 invd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 wbinvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 compatibility, floating-point and mmx instructions . . . . 191 configuration and initialization, power-on . . . . . . . . 167 , 291 connection requirements, pin . . . . . . . . . . . . . . . . . . . . . . 231 connections, power. . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 , 303 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 control unit, scheduler/instruction . . . . . . . . . . . . . . . . . . . . 9 counter, time stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 cycle, hold and hold acknowledge . . . . . . . . . . . . . . . . . . 136 cycle, shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 cycles bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 , 289 inquire . . . . . . . 79 C 84 , 94 , 98 C 99 , 112 , 116 , 132 , 136 , 138 . . . . . . . . . . . . . . . . .140 , 142 , 144 C 146 , 148 , 150 , 154 . . . . . . . . . . . . . . . . . . . . . . . . . 183 C 187 , 215 , 223 C 226 inquire and bus arbitration . . . . . . . . . . . . . . . . . . . . . . . 136 interrupt acknowledge . . . . . . . . . . 80 , 83 , 85 , 91 , 106 , 115 locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 , 81 pipelined write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 special bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 writeback . . . . . . . . . . . . . . . . . .79 , 81 C 82 , 95 , 98 , 116 , 132 . . . . . . . . . . . . . . . . . . . . . 140 , 144 , 146 , 148 , 150 , 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 C 175 , 216 , 226 d d/c# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 d[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 data bus . . . . . . . . . . . . . . . . . . . . 82 , 85 , 88 , 92 C 93 , 108 , 111 . . . . . . . . . . . . . . . . . . . . . . . . . .124 C 126 , 142 , 148 , 152 data cache, mesi states in the . . . . . . . . . . . . . . . . . . . . . 172 data parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 data types floating-point register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 data/code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 , 306 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 debug exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 , 216 dr3Cdr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 dr5Cdr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 decode, instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 decoupling recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 descriptions, signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 , 287 design, thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 , 313 designations, pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 , 317 device identification register . . . . . . . . . . . . . . . . . . 210 , 300 diagram, pin description . . . . . . . . . . . . . . . . . . . . . . 267 , 315 diagrams, timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 , 300 disabling, cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 dissipation, power . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 , 307 dp[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 dr3Cdr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 dr5Cdr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 drive strength, selectable . . . . . . . . . . . . . . . . . . . . . . . . . 237 e eads#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 efer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 eflags register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 , 305 environment, software . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 281 ewbe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 , 224 exception . . . . . 83 C 84 , 93 , 96 , 108 , 160 , 191 , 202 , 220 C 222 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 C 27 floating-point . . . . . . . . . . . . . . . . . . . . . . . 96 , 100 , 189 C 191 machine check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 exception handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 handling floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . 189 interrupts, and debug in smm . . . . . . . . . . . . . . . . . . . . 202 mmx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 execution unit, branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 execution unit, multimedia . . . . . . . . . . . . . . . . . . . . . . . . 191 execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 , 295 external address strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 external write buffer empty . . . . . . . . . . . . . . . . . . . . . . . . 95 extest instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
index 325 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information f ferr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 , 191 fetch, instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 float conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 , 288 floating-point and mmx instruction compatibility . . . . . . . . . . . . . . . . 191 and multimedia execution units . . . . . . . . . . . . . . . 189 , 295 error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 , 295 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 floating-point handling exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 flush# . . . . . . . . . . . . . . . . . . . . . . . . . 97 , 167 , 184 , 204 , 224 frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 , 242 , 253 operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 , 91 , 167 frequency multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 g gate descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 , 48 general-purpose registers . . . . . . . . . . . . . . . . . . . . . . 21 , 281 grounding, power and . . . . . . . . . . . . . . . . . . . . . . . . . 229 , 303 h halt state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 handling floating-point exceptions. . . . . . . . . . . . . . . . . . 189 heat dissipation path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 highz instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 history table, branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 hit to modified line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 hit to modified line, ahold-initiated inquire . . . . . . . . 146 hit to modified line, hold-initiated inquire . . . . . . . . . 140 hit to shared or exclusive line, ahold-initiated inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 hit to shared or exclusive line, hold-initiated inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 hit# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 hitm# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 , 237 C 238 hlda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 hold acknowledge . . . . . . . . . . . . . . . . . . . . . . . . .99 , 136 C 138 hold and hold acknowledge cycle . . . . . . . . . . . . . . . . . . 136 hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 , 255 hold-initiated inquire hit to modified line . . . . . . . . . . 140 hold-initiated inquire hit to shared or exclusive line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 i i/o buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 237 , 309 buffer model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 misaligned read and write . . . . . . . . . . . . . . . . . . . . . . . . 135 model application note. . . . . . . . . . . . . . . . . . . . . . . . . . . 239 read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 i/o buffer ac and dc characteristics . . . . . . . . . . . . . . . . 239 ibis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 idcode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 ieee 1149.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 , 205 , 277 , 300 ieee 754 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 , 25 , 189 , 277 ieee 854 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 , 25 , 189 , 277 ignne# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 , 191 ignore numeric exception . . . . . . . . . . . . . . . . . . . . . . . . . 100 init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 , 224 init, state of processor after . . . . . . . . . . . . . . . . . . . . . . 170 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 initialization, power-on configuration and . . . . . . . . 167 , 291 init-initiated transition from protected mode to real mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 input setup and hold timings for 60-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 input setup and hold timings for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 , 141 , 143 , 223 cycles. . . . . . . . . . . . . . . . . . . . . 79 C 84 , 94 , 98 C 99 , 112 , 116 . . . . . . . . . . . . . 132 , 136 , 138 , 140 , 142 , 144 C 146 , 148 . . . . . . . . . . . . . . . . . 150 , 154 , 183 C 187 , 215 , 223 C 226 inquire and bus arbitration cycles . . . . . . . . . . . . . . . . . . 136 inquire cycle hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 inquire cycle hit to modified line . . . . . . . . . . . . . . . . . . . 98 inquire cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 inquire miss, ahold-initiated . . . . . . . . . . . . . . . . . . . . . 142 instruction decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 instruction fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 instruction pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 instruction prefetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 instructions supported by the amd-k6 processor. . . 49 , 283 instructions, tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 integer data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 internal architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 279 internal snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 interrupt . . . . . . . . . . . . . . . . . . . 102 , 111 , 156 , 160 C 161 , 164 . . . . . . . . . . . . . . . . . 170 , 189 C 191 , 194 , 202 , 221 , 226 acknowledge cycles . . . . . . . . . . . . 80 , 83 , 85 , 91 , 106 , 115 descriptor table register . . . . . . . . . . . . . . . . . . . . . . . 39 C 40 flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 , 111 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 redirection bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 service routine . . . . . . . . . . . . . . . . . . . . . 102 , 106 , 190 , 193 system management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 interrupt acknowledge . . . . . . . . . . . . . . . . . . . 80 , 88 , 91 , 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 , 108 , 152 , 156 interrupt gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 interrupt, type of. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 interrupts 01h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 03h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 exceptions and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 intr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 irq13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 intr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 , 224 inv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 invalidation request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 invd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 k ken# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
326 index amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information l l1 cache inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 limit, write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 line fills, cache- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 lock# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 locked cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 locked operation with boff# intervention . . . . . . . . . . . 154 locked operation, basic . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 logic branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 branch-prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 C 19 external support of floating-point exceptions . . . . . . . . 189 symbol diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 , 285 m m/io# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 machine check exception . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 maskable interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 mcar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 , 170 mctr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 C 38 , 170 memory or i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 memory read and write, misaligned single-transfer . . . 128 memory read and write, single-transfer . . . . . . . . . . . . . 126 memory reads and writes. . . . . . . . . . . . . . . . . . . . . . . . . . 126 mesi. . . . . . . . . . . . . 5 , 11 , 136 , 140 , 172 , 182 , 185 , 187 , 277 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 , 172 C 173 states in the data cache . . . . . . . . . . . . . . . . . . . . . . . . . . 172 microarchitecture overview, amd-k6 processor . . . . . . . . . 7 microarchitecture, enhanced risc86 . . . . . . . . . . . . . . . . . . 8 misaligned i/o read and write. . . . . . . . . . . . . . . . . . . . . . 135 misaligned single-transfer memory read and write. . . . 128 mmx exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 instruction compatibility, floating-point and . . . . . . . . . 191 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mode, tri-state test . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 , 299 model 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 3 , 275 model 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 3 , 275 model-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 msr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 , 281 multimedia execution unit . . . . . . . . . . . . . . . . . . . . . . . . . 191 n na#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 next address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 nmi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 , 224 no-connect pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 , 231 non-maskable interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 non-pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 , 176 o operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 , 305 operation, cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 opn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 , 321 ordering part number . . . . . . . . . . . . . . . . . . . . . . . . . 273 , 321 organization, cache . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 , 293 output delay timings for 60-mhz bus operation . . . . . . . 248 output delay timings for 66-mhz bus operation . . . . . . . 244 output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 , 291 p package specifications . . . . . . . . . . . . . . . . . . . . . . . . 271 , 319 package thermal specifications . . . . . . . . . . . . . . . . 259 , 313 page cache disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 page directory entry (pde) . . . . . . . . . . . . . . . . . . 43 C 44 , 174 page table entry (pte). . . . . . . . . . . . . . . . . . . . . . 43 , 45 , 174 page writethrough. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 parity. . . . . . . . . . . . . . . . . . . . . . 77 , 83 , 85 , 93 , 108 , 126 , 285 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 , 93 , 108 check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 C 84 , 93 error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 , 108 , 142 , 206 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 part number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 , 321 pcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 , 174 , 180 pchk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 pin connection requirements . . . . . . . . . . . . . . . . . . . . . . 231 pin description diagram. . . . . . . . . . . . . . . . . . . . . . . 267 , 315 pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 , 317 pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 , 124 C 125 , 130 pipeline control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 pipeline, six-stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 C 9 pipelined. . . . . . . . . . . . 11 , 106 , 125 , 130 C 131 , 148 , 171 , 182 pipelined burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 pipelined cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 , 81 , 92 pipelined design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 pointer, instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 power and grounding . . . . . . . . . . . . . . . . . . . . . . . . . 229 , 303 power connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 , 303 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 , 307 power-on configuration and initialization . . . . . . . . 167 , 291 predecode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 C 12 , 172 prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 , 181 pwt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 r ranges, operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 , 305 ratings, absolute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 , 305 read and write, basic i/o. . . . . . . . . . . . . . . . . . . . . . . . . . 134 read and write, misaligned i/o. . . . . . . . . . . . . . . . . . . . . 135 reads, burst reads and pipelined burst. . . . . . . . . . . . . . 130 register boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 bypass (br). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 data types, floating-point . . . . . . . . . . . . . . . . . . . . . . . . . 28 debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 , 216 floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 general-purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 281 syscall/sysret target address (star) . . . . . . . . . 282 registers . . . . . . . . . . . . . . . . . . . . . . 9 , 21 , 168 , 191 , 281 , 291 descriptors and gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 device identification (dir) . . . . . . . . . . . . . . . . . . . 210 , 300 dr3Cdr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 dr5Cdr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 eflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 extended feature enable register (efer). . . . . . . . . . . 282
index 327 20695h/0march 1998 amd-k6 ? processor data sheet preliminary information ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 mcar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 memory management . . . . . . . . . . . . . . . . . . . . . . . . . 39 , 283 mmx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 star . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 tap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 , 300 tr12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 whcr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 , 283 regulator, voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 replacement, cache-line . . . . . . . . . . . . . . . . . . . . . . 177 , 184 requirements, pin connection . . . . . . . . . . . . . . . . . . . . . . 231 reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 , 168 , 224 and test signal timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 252 signals sampled during. . . . . . . . . . . . . . . . . . . . . . . . . . . 167 state of processor after. . . . . . . . . . . . . . . . . . . . . . . 168 , 291 return address stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 revision identifier, smm . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 risc86 microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 rsm instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 , 202 rsvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 s sample/preload instruction . . . . . . . . . . . . . . . . . . . . . 212 scheduler, centralized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 scheduler/instruction control unit . . . . . . . . . . . . . . . . . . . . 9 scyc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 sector, write to a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 segment descriptor . . . . . . . . . . . . . . . . . . . . . . . . . .24 , 45 C 47 segment registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 segment usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 segment, task state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 selectable drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . 237 shift-dr state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 shift-ir state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 shutdown cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 , 287 signal switching characteristics. . . . . . . . . . . . . . . . . 241 , 311 signal timing, reset and test . . . . . . . . . . . . . . . . . . . . . 252 signals a[20:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 C 238 a[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 a20m# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 , 194 ads# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 , 237 C 238 adsc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ahold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 , 224 ap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 apchk#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 be[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 bf[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 , 227 boff# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 , 150 brdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 brdyc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 , 237 breq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 cache#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 , 175 clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 d/c# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 d[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 dp[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 eads# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 ewbe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 , 224 ferr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 , 191 flush# . . . . . . . . . . . . . . . . . . . . . . 97 , 167 , 184 , 204 , 224 hit# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 hitm# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 , 237 C 238 hlda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ignne#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 , 191 init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 , 224 intr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 , 224 inv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ken# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 lock#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 m/io#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 na# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 , 224 pcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 pchk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 pwt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 , 224 rsvd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 scyc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 smi# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 , 193 , 224 smiact#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 , 193 stpclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 , 225 tck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 tdi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 tdo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 tms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 trst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 vcc2det . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 , 287 vcc2h/l#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 w/r# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 , 237 C 238 wb/wt# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 signals sampled during reset . . . . . . . . . . . . . . . . . . . . 167 signals, output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 , 291 signals, tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 single-transfer memory read and write . . . . . . . . . . . . . 126 smi# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 , 193 , 224 smiact#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 , 193 smm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 , 297 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 default register values. . . . . . . . . . . . . . . . . . . . . . . . . . . 193 halt restart slot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 i/o trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 i/o trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 state-save area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 snoop. . . . . . . . . . . . . . . . . . . . . . 112 , 116 , 132 , 183 , 185 C 186 snooping, cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 snooping, internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 software environment. . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 281 special bus cycle. . . . . . . . . . . . . 88 , 113 , 158 C 161 , 200 , 225 special bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 special cycle . . . . . . . . . . . . . . . . . 95 , 97 , 113 , 119 , 132 , 158 . . . . . . . . . . . . . . . . . . . . . . . . . . 160 C 161 , 176 , 224 C 225 specifications, package. . . . . . . . . . . . . . . . . . . . . . . . 271 , 319 specifications, package thermal . . . . . . . . . . . . . . . . 259 , 313 split cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 stack, return address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 state machine diagram, bus. . . . . . . . . . . . . . . . . . . . . . . . 123 state of processor after init . . . . . . . . . . . . . . . . . . . 170 , 291 state of processor after reset . . . . . . . . . . . . . . . . 168 , 291 states, cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 state-save area, smm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
328 index amd-k6 ? processor data sheet 20695h/0march 1998 preliminary information stop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 stop clock state . . . . . . . . . . . . . . . . . . . . . . . . . .161 , 226 C 227 stop grant inquire state . . . . . . . . . . . . . . . . . . . . . . . 223 C 226 stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . .161 , 225 C 226 stpclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 , 225 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 241 60-mhz bus operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 66-mhz bus operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 input setup and hold timings for 60-mhz bus . . . . . . . . 250 input setup and hold timings for 66-mhz bus . . . . . . . . 246 output delay timings for 60-mhz bus . . . . . . . . . . . . . . . 248 output delay timings for 66-mhz bus . . . . . . . . . . . . . . . 244 signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 , 311 valid delay, float, setup, and hold timings . . . . . . . . . . . 243 syscall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 C 283 syscall/sysret target address register (star) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 C 283 sysret . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 system design, airflow management in a . . . . . . . . . . . . . 264 system management interrupt . . . . . . . . . . . . . . . . . . . . . . 111 system management interrupt active . . . . . . . . . . . . . . . . 112 system management mode (smm) . . . . . . . . . . . . . . . 193 , 297 t table, branch history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 tap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 , 299 tap controller states capture-dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 capture-ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 shift-dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 shift-ir. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 test-logic-reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 update-dr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 update-ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 tap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 extest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 highz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 sample/preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 tap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 , 300 instruction register (ir) . . . . . . . . . . . . . . . . . . . . . . . . . 206 tap signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 target cache, branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 task state segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 tck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 tdi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 tdo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 temperature . . . . . . . . . . . . . . . . 233 , 259 C 260 , 262 , 305 , 313 case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 test access port, boundary-scan. . . . . . . . . . . . . . . . . 205 , 299 test and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 , 299 test clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 test data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 test data output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 test mode select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 test mode, tri-state . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 , 299 test register 12 (tr12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 test reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 test-logic-reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 , 260 C 264 , 307 design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 , 313 heat dissipation path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 layout and airflow consideration . . . . . . . . . . . . . . . . . . 262 measuring case temperature . . . . . . . . . . . . . . . . . . . . . 262 package specifications . . . . . . . . . . . . . . . . . . . . . . 259 , 313 time stamp counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 tms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 tr12 . . . . . . . . . . . . . . . . . . . . 37 C 38 , 170 , 174 C 175 , 180 , 215 transition from protected mode to real mode, init-initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 translation lookaside buffer (tlb) . . . . . . . . . . . . . . . . . 171 trap dword, i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 tri-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 , 299 trst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 tsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 C 38 , 170 , 224 C 225 tss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 , 47 C 48 , 197 , 220 v vcc2det . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 , 287 vcc2h/l#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 voltage . . . . . . . . . . . . . . . . 115 , 122 , 229 , 233 C 234 , 238 , 241 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 , 303 , 305 C 306 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 C 263 voltage ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 w w/r# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 , 237 C 238 wae15m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 waelim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 wb/wt# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 wbinvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 wcde . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 , 178 , 181 whcr . . . . . . . . . . . . . . . . . . . . . . . 37 , 39 , 170 , 179 , 181 , 283 write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 , 177 C 182 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 , 178 enable limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 , 178 limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 logic mechanisms and conditions . . . . . . . . . . . . . . . . . . 180 write handling control register (whcr) . . . . . . . . . 39 , 283 write to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . 178 write to a sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 write/read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 writeback . . . . . . . . . . . . . 90 , 92 C 93 , 103 , 109 , 112 , 116 , 119 . . . . . . . . .132 C 133 , 158 , 171 , 176 , 182 , 185 , 187 , 228 burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 cycles. . . . . . . . . . . . . . . . . . . . . 79 , 81 C 82 , 95 , 98 , 116 , 132 . . . . . . . . . . . . . . . . . . . . . 140 , 144 , 146 , 148 , 150 , 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 C 175 , 216 , 226 writeback cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 C 11 writeback or writethrough . . . . . . . . . . . . . . . . . . . . . . . . 116 writethrough vs. writeback coherency states. . . . . . . . . 187

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